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Numonyx B.V |
www.DataSheet4U.com
N25Q128
128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors,
XiP enabled, serial flash memory with 108 MHz SPI bus interface
Features
SPI-compatible serial bus interface
108 MHz (maximum) clock frequency
1.7 V to 2 V single supply voltage
Supports legacy SPI protocol and new Quad
I/O or Dual I/O SPI protocol
Quad/Dual I/O instructions resulting in an
equivalent clock frequency up to 432 MHz:
XIP mode for all three protocols
– Configurable via volatile or non-volatile
registers (enabling the memory to work in
XiP mode directly after power on)
Program/Erase suspend instructions
Continuous read of entire memory via single
instruction:
– Fast Read
– Quad or Dual Output Fast Read
– Quad or Dual I/O Fast Read
Flexible to fit application:
– Configurable number of dummy cycles
– Output buffer configurable
– Fast POR instruction: to speed up power
on phase
– Reset function available upon customer
request
64-byte user-lockable, one-time programmable
(OTP) area
Erase capability
– Subsector (4-Kbyte) granularity in the 8
boot sectors (bottom or top parts).
– Sector (64-Kbyte) granularity
Write protections
– Software write protection applicable to
every 64-Kbyte sector (volatile lock bit)
– Hardware write protection: protected area
size defined by five non-volatile bits (BP0,
BP1, BP2, BP3 and TB bit)
VDFPN8 (F8)
8 × 6 mm (MLP8)
SO16 (SF)
300 mils width
TBGA24 (12)
6 x 8 mm
– Additional smart protections available upon
customer request
Deep Power-down mode: 5 µA (typical)
Electronic signature
– JEDEC standard two-byte signature
(BB18h)
– Additional 2 Extended Device ID (EDID)
bytes to identify device factory options
– Unique ID code (UID) with 14 bytes read-
only, available upon customer request
100,000 + program/erase cycles per sector
More than 20 years data retention
Packages
– RoHS compliant
February 2010
Rev 1.0
1/185
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Contents
Contents
N25Q128 - 1.8 V
www.DataSheet4U.com
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 Serial data output (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Serial data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 Hold (HOLD) or Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6 Write protect/enhanced program supply voltage (W/VPP), DQ2 . . . . . . . 18
2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 SPI Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 Extended SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Dual I/O SPI (DIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 Quad SPI (QIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Extended SPI Protocol Operating features . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.2 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.3 Dual input fast program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.4 Dual Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.5 Quad Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.6 Quad Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.7 Subsector erase, sector erase and bulk erase . . . . . . . . . . . . . . . . . . . 24
5.1.8 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . 24
5.1.9 Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.10 Hold (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 Dual SPI (DIO-SPI) Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.1 Multiple Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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