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ADRF6601 반도체 회로 부품 판매점

300 MHz to 2500 MHz Rx Mixer



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Analog Devices
ADRF6601 데이터시트, 핀배열, 회로
Data Sheet
300 MHz to 2500 MHz Rx Mixer with
Integrated Fractional-N PLL and VCO
ADRF6601
FEATURES
Rx mixer with integrated fractional-N PLL
RF input frequency range: 300 MHz to 2500 MHz
Internal LO frequency range: 750 MHz to 1160 MHz
Input P1dB: 14.5 dBm
Input IP3: 31 dBm
IIP3 optimization via external pin
SSB noise figure
IP3SET pin open: 13.5 dB
IP3SET pin at 3.3 V: 14.6 dB
Voltage conversion gain: 6.7 dB
Matched 200 Ω IF output impedance
IF 3 dB bandwidth: 500 MHz
Programmable via 3-wire SPI interface
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Cellular base stations
GENERAL DESCRIPTION
The ADRF6601 is a high dynamic range active mixer with an
integrated phase-locked loop (PLL) and a voltage controlled
oscillator (VCO). The PLL/synthesizer uses a fractional-N
PLL to generate a fLO input to the mixer. The reference input
can be divided or multiplied and then applied to the PLL phase
frequency detector (PFD).
The PLL can support input reference frequencies from 12 MHz
to 160 MHz. The PFD output controls a charge pump whose
output drives an off-chip loop filter.
The loop filter output is then applied to an integrated VCO. The
VCO output at 2 × fLO is applied to an LO divider, as well as to a
programmable PLL divider. The programmable PLL divider is
controlled by a sigma-delta (Σ-Δ) modulator (SDM). The modulus
of the SDM can be programmed from 1 to 2047.
The active mixer converts the single-ended 50 Ω RF input to
a 200 Ω differential IF output. The IF output can operate up
to 500 MHz.
The ADRF6601 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, RoHS-compliant,
6 mm × 6 mm LFCSP with an exposed paddle. Performance is
specified over the −40°C to +85°C temperature range.
Table 1.
Part No.
ADRF6601
ADRF6602
ADRF6603
ADRF6604
Internal LO
Range
750 MHz
1160 MHz
1550 MHz
2150 MHz
2100 MHz
2600 MHz
2500 MHz
2900 MHz
±3 dB RFIN
Balun Range
300 MHz
2500 MHz
1000 MHz
3100 MHz
1100 MHz
3200 MHz
1200 MHz
3600 MHz
±1 dB RFIN
Balun Range
450 MHz
1600 MHz
1350 MHz
2750 MHz
1450 MHz
2850 MHz
1600 MHz
3200 MHz
LODRV_EN 36
LON 37
LOP 38
PLL_EN 16
DATA 12
CLK 13
LE 14
REF_IN 6
MUXOUT 8
FUNCTIONAL BLOCK DIAGRAM
VCC1
1
VCC2
10
VCC_LO
17
VCC_MIX VCC_V2I
22 27
VCC_LO
34
NC NC
32 33
ADRF6601
INTERNAL LO RANGE
750MHz TO 1160MHz
3.3V
LDO
BUFFER
2.5V
LDO
2 DECL3P3
9 DECL2P5
SPI
INTERFACE
×2
MUX
÷2
÷4
FRACTION
REG
MODULUS
INTEGER
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
21 TO 123
TEMP
SENSOR
+
PHASE
FREQUENCY
DETECTOR
BUFFER
PRESCALER
÷2
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
2:1
MUX
DIV
BY
4, 2, 1
VCO
CORE
VCO
LDO
40 DECLVCO
26 RFIN
29 IP3SET
4 7 11 15 20 21 23 24 25 28 30 31 35
GND
5
RSET
3 39
18 19
CP VTUNE IFP IFN
Figure 1.
Rev. B
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


ADRF6601 데이터시트, 핀배열, 회로
ADRF6601
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
RF Specifications .......................................................................... 3
Register 3—Σ-Δ Modulator Dither Control (Default:
0x10000B).................................................................................... 17
Register 4—PLL Charge Pump, PFD, and Reference Path
Control (Default: 0x0AA7E4)................................................... 18
Register 5—PLL Enable and LO Path Control (Default:
0x0000E5).................................................................................... 19
Register 6—VCO Control and VCO Enable (Default:
0x1E2106).................................................................................... 19
Synthesizer/PLL Specifications................................................... 4
Logic Input and Power Specifications ....................................... 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
RF Frequency Sweep .................................................................... 9
IF Frequency Sweep ................................................................... 10
Spurious Performance................................................................ 15
Register Structure ........................................................................... 16
Register 0—Integer Divide Control (Default: 0x0001C0) .... 16
Register 1—Modulus Divide Control (Default: 0x003001) ........16
Register 2—Fractional Divide Control (Default: 0x001802) ......17
REVISION HISTORY
Register 7—Mixer Bias Enable and External VCO Enable
(Default: 0x000007).................................................................... 19
Theory of Operation ...................................................................... 20
Programming the ADRF6601................................................... 20
Initialization Sequence .............................................................. 20
LO Selection Logic ..................................................................... 21
Applications Information .............................................................. 22
Basic Connections for Operation............................................. 22
AC Test Fixture ............................................................................... 23
Evaluation Board ............................................................................ 24
Evaluation Board Control Software......................................... 24
Schematic and Artwork............................................................. 26
Evaluation Board Configuration Options............................... 28
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
1/14—Rev. A to Rev. B
Replaced LO Range with RF Range in Data Sheet Title.............. 1
Updated Outline Dimensions ....................................................... 29
3/11—Rev. 0 to Rev. A
Changes to Features Section, General Description Section, and
Table 1 ............................................................................................ 1
Changes to Table 2............................................................................ 3
Changes to Conditions Statement and the Figure of Merit,
Reference Spurs, and Phase Noise Parameters, Table 3;
Changes to Conditions Statement and the Supply Current
Parameter, Table 4 ........................................................................ 4
Changes to Table 6............................................................................ 6
Changes to Table 7............................................................................ 7
Replaced Typical Performance Characteristics Section .............. 9
Added Spurious Performance Section......................................... 15
Changes to Figure 44 and Figure 45............................................. 19
Changes to Theory of Operation Section.................................... 20
Added AC Test Fixture Section and Figure 47;
Renumbered Sequentially ......................................................... 23
Changes to Evaluation Board Control Software Section........... 24
Changes to Table 10........................................................................ 28
1/10—Revision 0: Initial Version
Rev. B | Page 2 of 32




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