QL1P150 반도체 회로 부품 판매점
Ultra-Low Power FPGA Combining Performance
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 QuickLogic |
QuickLogic PolarPro™ Data Sheet
www.DataSheet4U.com
• • • • • • Combining Low Power, Performance, Density, and Embedded RAM
Device Highlights
Flexible Programmable Logic
• 0.18 µm, six layer metal CMOS process
• 1.8 V core voltage, 1.8/2.5/3.3 V drive
capable I/Os
• Up to 202 kilobits of SRAM
• Up to 292 I/Os available
• Up to one million system gates
• Nonvolatile, instant-on
• IEEE 1149.1 boundary scan testing compliant
Embedded Dual Port SRAM
• Up to eight dual-port 4-kilobit high performance
SRAM blocks
• Embedded synchronous/asynchronous FIFO
controller
• Configurable and cascadable aspect ratio
Programmable I/O
• Bank programmable drive strength
• Bank programmable slew rate control
• Independent I/O banks capable of supporting
multiple I/O standards in one device
• Native support for DDR I/Os
• Bank programmable I/O standards: LVTTL,
LVCMOS, and LVCMOS18
• Quadrant-based segmentable clock networks
20 quad clock networks per device
4 quad clock networks per quadrant
1 dedicated clock network per quadrant
• Two user Configurable Clock Managers (CCMs)
Very Low Power (VLP) Mode
• QuickLogic PolarPro has a special VLP pin which
can enable a low power sleep mode that
significantly reduces the overall power
consumption of the device.
• Enter VLP mode from normal operation in less
than 250 µs
• Exit from VLP mode to normal operation in less
than 250 µs
Security Links
There are several security links to disable JTAG
access to the device. Programming these optional
links completely disables access to the device from
the outside world and provides an extra level of
design security not possible in SRAM-based FPGAs.
Figure 1: QuickLogic PolarPro Block Diagram
CCM DDR/GPIO
DDR/GPIO
DDR/GPIO
Embedded RAM Blocks
FIFO Controller
DDR/GPIO CCM
Fabric
Advanced Clock Network
• Multiple low skew clock networks
1 dedicated global clock network
4 programmable global clock networks
GPIO
FIFO Controller
Embedded RAM Blocks
GPIO
GPIO
GPIO
© 2005 QuickLogic Corporation
PRELIMINARY
www.quicklogic.com ••••••
1
QuickLogic PolarPro™ Data Sheet Rev. A
www.DataSheet4U.com
Ultra-Low Power FPGA Combining Performance, Density, and
Embedded RAM
Features
Max Gates
Logic Cells
Max I/O
RAM Modules
FIFO Controllers
RAM bits
CCMs
TFBGA (0.8 mm)
Packages TQFP (0.5 mm)
LBGA (1.0 mm)
Table 1: PolarPro Product Family Members
QL1P075 QL1P100 QL1P150 QL1P300
75,000
512
172
100,000
640
188
150,000
1,536
292
300,000
1,920
302
8
8
36,864
8
8
36,864
12
12
55,296
12
12
55,296
22
196 196
2
-
2
-
144 144
-
-
256 256 256, 324 256, 324
QL1P600
600,000
4,224
508
22
22
202,752
2
-
-
256, 324
QL1P1000
1,000,000
7,680
652
22
22
202,752
2
-
-
256, 324
Process Data
QuickLogic PolarPro is fabricated on a 0.18 µ, six layer metal CMOS process. The core voltage is 1.8 V. The
I/O voltage input tolerance and output drive can be set as 1.8 V, 2.5 V, and 3.3 V.
Programmable Logic Architectural Overview
The QuickLogic PolarPro logic cell structure presented in Figure 2 is a single register, multiplexer-based logic
cell. It is designed for wide fan-in and multiple, simultaneous output functions. The cell has a high fan-in, fits
a wide range of functions with up to 24 simultaneous inputs (including register control lines), and four outputs
(three combinatorial and one registered). The high logic capacity and fan-in of the logic cell accommodates
many user functions with a single level of logic delay.
The QuickLogic PolarPro logic cell can implement:
• Two independent 3-input functions
• Any 4-input function
• 8 to 1 mux function
• Independent 2 to 1 mux function
• Single dedicated register with clock enable, active high set and reset signals
• Direct input selection to the register, which allows combinatorial and register logic to be used separately
• Combinatorial logic that can also be configured as an edge-triggered master-slave D flip-flop
2 •••••• www.quicklogic.com
PRELIMINARY
© 2005 QuickLogic Corporation
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