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PH1875L 반도체 회로 부품 판매점

N-channel TrenchMOS logic level FET



NXP Semiconductors 로고
NXP Semiconductors
PH1875L 데이터시트, 핀배열, 회로
PH1875L
www.DataSheet4U.com
N-channel TrenchMOS logic level FET
Rev. 01 — 29 November 2005
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
s Logic level threshold
s Low thermal resistance
s Very low on-state resistance
s Surface-mounted package
1.3 Applications
s DC motor control
s DC-to-DC converters
s General purpose power switching
1.4 Quick reference data
s VDS 75 V
s RDSon 16.5 m
s ID 45.8 A
s QGD = 15.3 nC (typ)
2. Pinning information
Table 1: Pinning
Pin Description
1, 2, 3 source (S)
4 gate (G)
mb mounting base; connected to drain (D)
Simplified outline
mb
1234
SOT669 (LFPAK)
Symbol
D
G
mbb076 S


PH1875L 데이터시트, 핀배열, 회로
Philips Semiconductors
PH1875L
www.DataSheet4U.com
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2: Ordering information
Type number
Package
Name
Description
PH1875L
LFPAK
plastic single-ended surface mounted package; 4 leads
4. Limiting values
Version
SOT669
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min Max Unit
VDS
VDGR
VGS
ID
drain-source voltage
drain-gate voltage (DC)
gate-source voltage
drain current
IDM peak drain current
Ptot total power dissipation
Tstg storage temperature
Tj junction temperature
Source-drain diode
25 °C Tj 150 °C
- 75 V
25 °C Tj 150 °C; RGS = 20 k
- 75 V
- ±15 V
Tmb = 25 °C; VGS = 10 V; see Figure 2 and 3
-
45.8 A
Tmb = 100 °C; VGS = 10 V; see Figure 2
- 29 A
Tmb = 25 °C; pulsed; tp 10 µs; see Figure 3
-
183 A
Tmb = 25 °C; see Figure 1
- 62.5 W
55 +150 °C
55 +150 °C
IS source current
ISM peak source current
Avalanche ruggedness
Tmb = 25 °C
Tmb = 25 °C; pulsed; tp 10 µs
- 45.8 A
- 183 A
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 26 A;
tp = 0.11 ms; VDS 75 V; RGS = 50 ;
VGS = 10 V; starting at Tj = 25 °C
- 165 mJ
PH1875L_1
Product data sheet
Rev. 01 — 29 November 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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N-channel TrenchMOS logic level FET - NXP Semiconductors