파트넘버.co.kr ICS673-01 데이터시트 PDF


ICS673-01 반도체 회로 부품 판매점

PLL Building Block



Integrated Circuit Systems 로고
Integrated Circuit Systems
ICS673-01 데이터시트, 핀배열, 회로
ICS673-01
PLL Building Block
Description
The ICS673-01 is a low cost, high performance
Phase Locked Loop (PLL) designed for clock
synthesis and synchronization. Included on the
chip are the phase detector, charge pump, Voltage
Controlled Oscillator (VCO), and two output
buffers. One output buffer is a divide by two of
the other. Through the use of external reference
and VCO dividers (easily implemented with the
www.IDCaSta6S7h4ee-0t41U).c, otmhe user can easily customize the
clock to lock to a wide variety of input frequencies.
Included on the ICS673-01 are an Output Enable
function that puts both outputs into a high-
impedance state, as well as a Power Down feature
that turns off the entire device.
Features
• Packaged in 16 pin narrow SOIC
• Access to VCO input and feedback paths of PLL
• VCO operating range up to 135 MHz (5V)
• Able to lock MHz range outputs to kHz range
inputs through use of external dividers
• Output Enable tri-states outputs
• Low skew output clocks
• Power Down turns off chip
• VCO predivide of 1 or 4
• 25 mA output drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• +3.3 V ±5% or +5 V ±10% operating voltage
• Industrial Temperature range available
• With the ICS674-01, forms a complete PLL
Block Diagram
VDD GND
23
CHGP VCOIN
VDD
REFIN
FBIN
PD
(entire chip)
Ic
Phase/ UP
Frequency
Detector
DOWN
Ic
VCO
1
MUX
÷4 0
Output
Buffer
÷2
Output
Buffer
CLK1
CLK2
CAP
SEL OE (both outputs)
MDS 673-01 D
1
Revision 022500
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com


ICS673-01 데이터시트, 핀배열, 회로
Pin Assignment
ICS673-01
FBIN 1 16 REFIN
VDD 2 15 N C
VDD 3 14 CLK1
GND 4 13 CLK2
w w w . D a Gt NaDS h 5e e t 142 U .PcD o m
GND 6 11 SEL
CHGP 7 10 OE
VCOIN 8 9 CAP
16 pin narrow (150 mil) SOIC
ICS673-01
PLL Building Block
VCO Predivide Select Table
SEL VCO Predivide
04
11
0 = connect pin directly to ground
1 = connect pin directly to VDD
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
FBIN
VDD
VDD
GND
GND
GND
CHGP
VCOIN
CAP
OE
SEL
PD
CLK2
CLK1
NC
REFIN
Type
CI
P
P
P
P
P
O
I
I
I
I
I
O
O
-
CI
Description
FeedBack INput. Connect feedback clock to this pin. Falling edge triggered.
VDD. Connect to +3.3 V or +5 V, and to VDD on pin 3.
VDD. Connect to VDD on pin 2.
Connect to ground.
Connect to ground.
Connect to ground.
CHarGe Pump output. Connect to VCOIN under normal operation.
Input to internal VCO.
Loop filter return.
Output Enable. Active high. Tri-states both outputs when low.
SELect pin for VCO pre-divide per table above.
Power Down. Turns off entire chip when this pin is low. Outputs stop low.
CLocK output 2. This is a low-skew divide by two version of CLK1.
CLocK output 1.
No Connect. Nothing is connected internally to this pin.
REFerence INput. Connect reference clock to this pin. Falling edge triggered.
Key: CI = clock input, I = Input, O = output, P = power supply connection
MDS 673-01 D
2
Revision 022500
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com




PDF 파일 내의 페이지 : 총 9 페이지

제조업체: Integrated Circuit Systems

( integrated )

ICS673-01 data

데이터시트 다운로드
:

[ ICS673-01.PDF ]

[ ICS673-01 다른 제조사 검색 ]




국내 전력반도체 판매점


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877

[ 홈페이지 ]

IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈

( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )

전력반도체 문의 : 010-3582-2743



일반적인 전자부품 판매점


디바이스마트

IC114

엘레파츠

ICbanQ

Mouser Electronics

DigiKey Electronics

Element14


관련 데이터시트


ICS673-01

PLL Building Block - Integrated Circuit Systems