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PDF RD74LVC1G79 Data sheet ( Hoja de datos )
| Número de pieza | RD74LVC1G79 | |
| Descripción | Single Positive Edge-triggered D-type Flip Flop | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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RD74LVC1G79
www.DataSheet4U.com
Single Positive Edge-triggered D-type Flip Flop
Description
REJ03D0695–0100
Rev.1.00
Feb 23, 2006
The RD74LVC1G79 has D-type flip flop in a 5-pin package. The input data is transferred to the output at the rising
edge of clock pulse CLK. Low voltage and high-speed operation is suitable for the battery powered products (e.g.,
notebook computers), and the low power consumption extends the battery life.
Features
• The basic gate function is lined up as Renesas uni logic series.
• Supply voltage range: 1.65 to 5.5 V
• Operating temperature range: –40 to +85°C
• All inputs: VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs: VO (Max.) = 5.5 V (@VCC = 0 V)
• Output current:
±4 mA (@VCC = 1.65 V)
±8 mA (@VCC = 2.3 V)
±24 mA (@VCC = 3.0 V)
±32 mA (@VCC = 4.5 V)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
RD74LVC1G79WPE
WCSP-5 pin
SXBG0005LB–A
(TBS-5CV)
Package
Abbreviation
WP
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Article Indication
Marking
Year code
Month code
EF YM
Rev.1.00 Feb 23, 2006 page 1 of 6
1 page  
RD74LVC1G79
Switching Characteristics
www.DataSheet4U.com
VCC = 1.8±0.15 V
FROM
TO
Item
Symbol Min Typ Max Unit Test conditions (Input) (Output)
Maximum clock frequency
fmax
160
MHz CL = 30 pF
Propagation delay time
tPLH, tPHL
4.4
9.9
ns CL = 30 pF
Setup time
tsu 2.2 ns
CLK Q
D
Hold time
th 0.3 ns
Pulse width
tw 2.5 ns
CLK “H” or “L”
VCC = 2.5±0.2 V
FROM
TO
Item
Symbol Min Typ Max Unit Test conditions (Input) (Output)
Maximum clock frequency
fmax
160
MHz CL = 30 pF
Propagation delay time
tPLH, tPHL
2.3
7.0
ns CL = 30 pF
CLK Q
Setup time
tsu 1.4 ns
D
Hold time
th 0.4 ns
Pulse width
tw 2.5 ns
CLK “H” or “L”
VCC = 3.3±0.3 V
FROM
TO
Item
Symbol Min Typ Max Unit Test conditions (Input) (Output)
Maximum clock frequency
fmax
160
MHz CL = 50 pF
Propagation delay time
tPLH, tPHL
2.0
5.0
ns CL = 50 pF
CLK Q
Setup time
tsu 1.3 ns
D
Hold time
th 1.0 ns
Pulse width
tw 2.5 ns
CLK “H” or “L”
VCC = 5.0±0.5 V
FROM
TO
Item
Symbol Min Typ Max Unit Test conditions (Input) (Output)
Maximum clock frequency
fmax
160
MHz CL = 50 pF
Propagation delay time
tPLH, tPHL
1.3
4.5
ns CL = 50 pF
Setup time
tsu 1.2 ns
CLK Q
D
Hold time
th 0.5 ns
Pulse width
tw 2.5 ns
CLK “H” or “L”
Operating Characteristics
Item
Power dissipation capacitance
Symbol
CPD
VCC (V)
1.8
2.5
3.3
5.0
Ta = 25°C
Min Typ Max
— 20 —
— 21 —
— 22 —
— 26 —
Unit Test Conditions
pF f = 10 MHz
Rev.1.00 Feb 23, 2006 page 5 of 8
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet RD74LVC1G79.PDF ] | |
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