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LX128B-5F208C 반도체 회로 부품 판매점

High Performance Interfacing and Switching



Lattice Semiconductor 로고
Lattice Semiconductor
LX128B-5F208C 데이터시트, 핀배열, 회로
www.DataSheet4U.com
ispGDX2Family
Includes
High-
High Performance Interfacing and Switching
September 2005
Features
Performance,
Low-Cost
“E-Series” Two Options Available
Data Sheet
• High-performance sysHSI (standard part number)
High Performance Bus Switching
• Low-cost, no sysHSI (“E-Series”)
• High bandwidth
– Up to 12.8 Gbps (SERDES)
sysHSI Blocks Provide up to 16 High-speed
– Up to 38 Gbps (without SERDES)
Channels
• Up to 16 (15x10) FIFOs for data buffering
• Serializer/de-serializer (SERDES) included
• High speed performance
• Clock Data Recovery (CDR) built in
– fMAX = 360MHz
– tPD = 3.0ns
– tCO = 2.9ns
– tS = 2.0ns
• Built-in programmable control logic capability
• 800 Mbps per channel
• LVDS differential support
• 10B/12B support
– Encoding / decoding
– Bit alignment
• I/O intensive: 64 to 256 I/Os
– Symbol alignment
• Expanded MUX capability up to 188:1 MUX
• 8B/10B support
– Bit alignment
sysCLOCK™ PLL
– Symbol alignment
• Frequency synthesis and skew management
• Source Synchronous support
• Clock multiply and divide capability
• Clock shifting up to +/-2.35ns in 335ps steps
Flexible Programming and Testing
• Up to four PLLs
• IEEE 1532 compliant In-System Programmabil-
ity (ISP™)
sysIO™ Interfacing
• Boundary scan test through IEEE 1149.1
• LVCMOS 1.8, 2.5, 3.3 and LVTTL support for
interface
standard board interfaces
• 3.3V, 2.5V or 1.8V power supplies
• SSTL 2/3 Class I and II support
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
• HSTL Class I, III and IV support
interfaces
• GTL+, PCI-X for bus interfaces
• LVPECL, LVDS and Bus LVDS differential support
• Hot socketing
• Programmable drive strength
Table 1. ispGDX2 Family Selection Guide
ispGDX2-64/E
ispGDX2-128/E
ispGDX2-256/E
I/Os 64 128 256
GDX Blocks
4 8 16
tPD
tS
tCO
fMAX (Toggle)
Max Bandwidth
sysHSI Channels2
SERDES1, 2
Without SERDES3
3.0ns
2.0ns
2.9ns
360MHz
3.2Gbps
11Gbps
4
3.2ns
2.0ns
3.1ns
330MHz
6.4Gbps
21Gbps
8
3.5ns
2.0ns
3.2ns
300MHz
12.8Gbps
38Gbps
16
LVDS/Bus LVDS (Pairs)
32 64 128
PLLs
224
Package
100-ball fpBGA
208-ball fpBGA
484-ball fpBGA
1. Max number of SERDES channels per device * 800Mbps
2. “E-Series” does not support sysHSI.
3. fMAX (Toggle) * maximum I/Os divided by 2.
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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gdx2fam_13


LX128B-5F208C 데이터시트, 핀배열, 회로
Lattice Semiconductor
Figure 1. ispGDX2 Block Diagram (256-I/O Device)
ispGDX2 Fwawmwi.lDyatDaSahteaetS4Uh.ceoemt
sysIO Bank
sysIO Bank
sysCLOCK
PLL
sysHSI
Block
SERDES
FIFO
SERDES
FIFO
SERDES
FIFO
SERDES
sysHSI
Block
FIFO
sysCLOCK
PLL
GDX Block GDX Block GDX Block GDX Block
Global Routing Pool
(GRP)
GDX Block GDX Block GDX Block GDX Block
sysCLOCK
PLL
FIFO
sysHSI
Block
SERDES
FIFO
SERDES
sysIO Bank
FIFO
SERDES
FIFO
SERDES
sysHSI
Block
sysCLOCK
PLL
sysIO Bank
ISP & Boundary Scan
Test Port
Introduction
The ispGDX2™ family is Lattice’s second generation in-system programmable generic digital crosspoint switch for
high speed bus switching and interface applications.
The ispGDX2 family is available in two options. The standard device supports sysHSI capability for ultra fast serial
communications while the lower-cost “E-series” supports the same high-performance FPGA fabric without the
sysHSI Block.
This family of switches combines a flexible switching architecture with advanced sysIO interfaces including high
performance sysHSI Blocks, and sysCLOCK PLLs to meet the needs of the today’s high-speed systems. Through
a muliplexer-intensive architecture, the ispGDX2 facilitates a variety of common switching functions.
The availability of on-chip control logic further enhances the power of these devices. A high-performance solution,
the family supports bandwidth up to 38Gbps.
Every device in the family has a number of PLLs to provide the system designer with the ability to generate multiple
clocks and manage clock skews in their systems.
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