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PDF ADRF6655 Data sheet ( Hoja de datos )
| Número de pieza | ADRF6655 | |
| Descripción | Broadband Up/Downconverting Mixer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Broadband Up/Downconvertwinwwg.DaMtaSihxeeet4rU.cwomith
Integrated Fractional-N PLL and VCO
ADRF6655
FEATURES
Broadband active mixer with integrated fractional-N PLL
RF input frequency range: 100 MHz to 2500 MHz
Internal LO frequency range: 1050 MHz to 2300 MHz
Flexible IF output interface
Input P1dB: 12 dBm
Input IP3: 29 dBm
Noise figure (SSB): 12 dB
Voltage conversion gain: 6 dB
Matched 200 Ω output impedance
SPI serial interface for PLL programming
40-lead 6 mm × 6 mm LFCSP
GENERAL DESCRIPTION
The ADRF6655 is a high dynamic range active mixer with
integrated PLL and VCO. The synthesizer uses a programmable
integer-N/fractional-N PLL to generate a local oscillator input
to the mixer. The PLL reference input is nominally 20 MHz. The
reference input can be divided by or multiplied by and then
applied to the PLL phase detector. The PLL can support input
reference frequencies from 10 MHz to 160 MHz. The phase
detector output controls a charge pump whose output is integrated
in an off-chip loop filter. The loop filter output is then applied to an
integrated VCO. The VCO output at 2 × fLO is then applied to a local
oscillator (LO) divider as well as to a programmable PLL divider.
The programmable divider is controlled by an Σ-Δ modulator
(SDM). The modulus of the SDM can be programmed between
1 and 2047.
The broadband, active mixer employs a bias adjustment to allow
for enhanced IP3 performance at the expense of increased supply
current. The mixer provides an input IP3 exceeding 25 dBm
with 12 dB single sideband NF under typical conditions. The IIP3
can be boosted to ~29 dBm with roughly 20 mA of additional
supplied current. The mixer provides a typical voltage conversion
gain of 6 dB with a 200 Ω differential IF output impedance. The
IF output can be externally matched to support upconversion over
a limited frequency range.
The ADRF6655 is fabricated using an advanced silicon-germanium
BiCMOS process. It is packaged in a 40-lead, exposed-paddle,
Pb-free, 6 mm × 6 mm LFCSP. Performance is specified over a
−40°C to +85°C temperature range.
LON 37
LOP 38
GND 11
DATA 12
CLK 13
LE 14
GND 15
REFIN 6
GND 7
MUXOUT 8
GND GND VCCLO
36 35
34
FUNCTIONAL BLOCK DIAGRAM
LOSEL
BUFFER
NC NC GND
33 32 31
ADRF6655
30 GND
29 IP3SET
28 GND
27 VCCMIX
SPI
INTERFACE
×2
MUX
÷2
÷4
FRACTION
REG
MODULUS
INTEGER
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
21 TO 123
BUFFER
LOSEL
PRESCALER
MUX
DIVIDER
÷2 OR ÷3
VCO
CORE
TEMP
SENSOR
–
+
PHASE
FREQUENCY
DETECTOR
3.3V LDO
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
2.5V LDO
VCO LDO
26 INP
25 INN
24 GND
23 GND
22 VCCV2I
21 GND
1
VCC1
2
DECL1
34
5
9 10 39 40 16 17 18 19 20
CP GND RSET DECL2 VCC2 VTUNE DECL3 NC VCCLO OUTN OUTP GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
TIMING CHARACTERISTICS
Table 2. Serial Interface Timing, VCC = 5 V ± 5%
Parameter
Limit
Unit
t1 20 ns minimum
t2 10 ns minimum
t3 10 ns minimum
t4 25 ns minimum
t5 25 ns minimum
t6 10 ns minimum
t7 20 ns minimum
ADRF6655www.DataSheet4U.com
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
CLK
DATA
DB23 (MSB)
LE
t4 t5
t2 t3
DB22
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
t7
t1
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 44
5 Page 
ADRF6655www.DataSheet4U.com
UPCONVERSION
Measured using typical upconversion circuit schematic with high-side LO and 340 MHz RF input, unless otherwise noted.
5
+25°C
4 –40°C
+85°C
3
2
1
0
–1
–2
–3
–4
–5
710 810 910 1010 1110 1210 1310 1410 1510 1610
OUTPUT FREQUENCY (MHz)
Figure 16. Conversion Gain vs. Output Frequency
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
710
IP3SET = 3.2V
IP3SET = OPEN
+25°C
–40°C
+85°C
810 910 1010 1110 1210 1310 1410 1510 1610
OUTPUT FREQUENCY (MHz)
Figure 19. Output IP3 vs. Output Frequency
0
+25°C
–10 –40°C
+85°C
–20
–30
–40
–50
–60
–70
–80
–90
–100
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250
LO FREQUENCY (MHz)
Figure 17. fLO − 2 × fRF Spurious Response vs.
LO Frequency (Relative to IF Output Power)
0
+25°C
–10
–40°C
+85°C
–20
–30
–40
–50
–60
–70
–80
1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050
LO FREQUENCY (MHz)
Figure 18. LO-to-IF Output Leakage vs. Frequency
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
710
IP3SET = 3.2V
IP3SET = OPEN
+25°C
–40°C
+85°C
810 910 1010 1110 1210 1310 1410 1510 1610
OUTPUT FREQUENCY (MHz)
Figure 20. Output P1dB vs. Output Frequency
–100
–110
–120
–130
–140
–150
–160
–170
710 810 910 1010 1110 1210 1310 1410 1510 1610
OUTPUT FREQUENCY (MHz)
Figure 21. Output Noise Spectral Density vs. Output Frequency
Rev. 0 | Page 11 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADRF6655.PDF ] | |
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