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CG6264AM 반도체 회로 부품 판매점

2Mb (128K x 16) Pseudo Static RAM



Weida Semiconductor 로고
Weida Semiconductor
CG6264AM 데이터시트, 핀배열, 회로
ADVANCE INFORMATION
CG6264AM
2Mb (128K x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.70V–3.30V
• Access Time: 70ns
• Ultra-low active power
— Typical active current: 2.0mA @ f = 1 MHz
— Typical active current: 13mA @ f = fmax
• Ultra low standby power
• Easy memory expansion with CE, CE2, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48 Ball BGA Package
Functional Description[1]
The CG6264AM is a high-performance CMOS Pseudo static
RAM organized as 128K words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life® (MoBL) in
portable applications such as cellular telephones. The device
can be put into standby mode reducing power consumption by
more than 99% The device can also be put into standby mode
when deselected (CE HIGH or CE2 LOW or both BHE and BLE
are HIGH). The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected (CEHIGH
or CE2 LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW, CE2 HIGH and WE
LOW). The addresses must not be toggled once the read
is started on the device.
Writing to the device is accomplished by taking Chip Enables
(CE LOW and CE2 HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A17). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enables (CE LOW and CE2 HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. See the truth table at the back of this
datasheet for a complete description of read and write modes
Logic Block Diagram
www.DataSheet4U.com
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
128K × 16
RAM Array
COLUMN DECODER
I/O0 – I/O7
I/O8 – I/O15
BHE
WE
OE
CE2
CE
BLE
Power- Down
Circuit
BHE
BLE
CE2
CE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Weida Semiconductor, Inc.
38-XXXXX
Revised Feb 2004


CG6264AM 데이터시트, 핀배열, 회로
Pin Configuration[2, 3, 4]
ADVANCE INFORMATION
FBGA
Top View
12 34 56
BLE OE A0 A1 A2 CE2
I/O8 BHE A3 A4 CE I/O0
I/O9 I/O10 A5 A6 I/O1 I/O2
VSS I/O11 NC A7 I/O3 Vcc
VCC I/O12 GND A16 I/O4 Vss
I/O14 I/O13 A14 A15 I/O5 I/O6
I/O15 NC
NC A8
A12 A13 WE I/O7
A9 A10 A11 NC/
A
B
C
D
E
F
G
H
Note:
2. NC “no connect” - not connected internally to the die.
3. DNU pins are to be left floating or tied to Vss.
4. Ball D3, H1, G2 and H6 are the expansion pins for the 4Mb, 8Mb,16Mb and 32Mb density resectively.
CG6264AM
www.DataSheet4U.com
38-XXXXX
Page - 2 - of 12




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CG6264AM

2Mb (128K x 16) Pseudo Static RAM - Weida Semiconductor