파트넘버.co.kr FSB50550US 데이터시트 PDF


FSB50550US 반도체 회로 부품 판매점

Smart Power Module



Fairchild Semiconductor 로고
Fairchild Semiconductor
FSB50550US 데이터시트, 핀배열, 회로
February 2009
FSB50550US
Smart Power Module (SPM®)
Features
• 500V RDS(on)=1.4Ω(max) 3-phase FRFET inverter including
high voltage integrated circuit (HVIC)
• 3 divided negative dc-link terminals for inverter current sens-
ing applications
• HVIC for gate driving and undervoltage protection
• 3/5V CMOS/TTL compatible, active-high interface
• Optimized for low electromagnetic interference
• Isolation voltage rating of 1500Vrms for 1min.
• Surface mounted device package
• Moisture Sensitive Level (MSL) 3
General Description
FSB50550US is a tiny smart power module (SPM®) based on
FRFET technology as a compact inverter solution for small
power motor drive applications such as fan motors and water
suppliers. It is composed of 6 fast-recovery MOSFET (FRFET),
and 3 half-bridge HVICs for FRFET gate driving. FSB50550US
provides low electromagnetic interference (EMI) characteristics
with optimized switching speed. Moreover, since it employs
FRFET as a power switch, it has much better ruggedness and
larger safe operation area (SOA) than that of an IGBT-based
power module or one-chip solution. The package is optimized
for the thermal performance and compactness for the use in the
built-in motor application and any other application where the
assembly space is concerned. FSB50550US is the most
solution for the compact inverter providing the energy efficiency,
compactness, and low electromagnetic interference.
www.DataAShbeseto4Ul.ucotme Maximum Ratings
Symbol
Parameter
VPN
DC Link Input Voltage,
Drain-source Voltage of each FRFET
ID25 Each FRFET Drain Current, Continuous
ID80 Each FRFET Drain Current, Continuous
IDP Each FRFET Drain Current, Peak
PD Maximum Power Dissipation
VCC Control Supply Voltage
VBS High-side Bias Voltage
VIN Input Signal Voltage
TJ Operating Junction Temperature
TSTG Storage Temperature
RθJC Junction to Case Thermal Resistance
VISO Isolation Voltage
Conditions
Rating
500
TC = 25°C
TC = 80°C
TC = 25°C, PW < 100μs
TC = 25°C, Each FRFET
Applied between VCC and COM
Applied between VB(U)-U, VB(V)-V, VB(W)-W
Applied between IN and COM
2.0
1.5
5
14.5
20
20
-0.3 ~ VCC+0.3
-40 ~ 150
Each FRFET under inverter operating con-
dition (Note 1)
-50 ~ 150
8.6
60Hz, Sinusoidal, 1 minute, Connection
pins to heatsink
1500
Units
V
A
A
A
W
V
V
V
°C
°C
°C/W
Vrms
©2009 Fairchild Semiconductor Corporation
FSB50550US Rev. A
1
www.fairchildsemi.com


FSB50550US 데이터시트, 핀배열, 회로
Pin Descriptions
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Pin Name
COM
VB(U)
VCC(U)
IN(UH)
IN(UL)
VS(U)
VB(V)
VCC(V)
IN(VH)
IN(VL)
VS(V)
VB(W)
VCC(W)
IN(WH)
IN(WL)
VS(W)
P
U
NU
NV
V
NW
W
Pin Description
IC Common Supply Ground
Bias Voltage for U Phase High Side FRFET Driving
Bias Voltage for U Phase IC and Low Side FRFET Driving
Signal Input for U Phase High-side
Signal Input for U Phase Low-side
Bias Voltage Ground for U Phase High Side FRFET Driving
Bias Voltage for V Phase High Side FRFET Driving
Bias Voltage for V Phase IC and Low Side FRFET Driving
Signal Input for V Phase High-side
Signal Input for V Phase Low-side
Bias Voltage Ground for V Phase High Side FRFET Driving
Bias Voltage for W Phase High Side FRFET Driving
Bias Voltage for W Phase IC and Low Side FRFET Driving
Signal Input for W Phase High-side
Signal Input for W Phase Low-side
Bias Voltage Ground for W Phase High Side FRFET Driving
Positive DC–Link Input
Output for U Phase
Negative DC–Link Input for U Phase
Negative DC–Link Input for V Phase
Output for V Phase
Negative DC–Link Input for W Phase
Output for W Phase
www.DataSheet4U.com
(1) COM
(2) VB(U)
(3) VCC(U)
(4) IN(UH)
(5) IN(UL)
(6) VS(U)
(7) VB(V)
(8) VCC(V)
(9) IN(VH)
(10) IN(VL)
(11) VS(V)
(12) VB(W)
(13) VCC(W)
(14) IN(WH)
(15) IN(WL)
(16) VS(W)
VCC
HIN
LIN
COM
VB
HO
VS
LO
VCC
HIN
LIN
COM
VB
HO
VS
LO
VCC
HIN
LIN
COM
VB
HO
VS
LO
(17) P
(18) U
(19) NU
(20) NV
(21) V
(22) NW
(23) W
Note:
Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside SPM®. External connections should be made as indicated in Fig-
ure 2 and 5.
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
FSB50550US Rev. A
2
www.fairchildsemi.com




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