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Número de pieza | L24C32 | |
Descripción | (L24C32 / L24C64) Two Wire Serial EEPROM | |
Fabricantes | Sigma | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de L24C32 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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SPECIFICATION
L24C32/L24C64
Version 1.0
Sigma reserves the right to change this documentation without prior notice.
Features
1 page L24C32/L24C64
32K bits (4096 X 8) / 64K bits (8192 X 8)
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part
can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
Figure 1: Data Validity
Figure 2: Start and Stop Definition
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Figure 3: Output Acknowledge
Page 5 of 14
5 Page Bus Timing
Figure 10: SCL: Serial Clock, SDA: Serial Data I/O
L24C32/L24C64
32K bits (4096 X 8) / 64K bits (8192 X 8)
Write Cycle Timing
Figure 11: SCL: Serial Clock, SDA: Serial Data I/O
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Note
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the
internal clear/write cycle.
Page 11 of 14
11 Page |
Páginas | Total 14 Páginas | |
PDF Descargar | [ Datasheet L24C32.PDF ] |
Número de pieza | Descripción | Fabricantes |
L24C32 | (L24C32 / L24C64) Two Wire Serial EEPROM | Sigma |
L24C32A | 32K bits EEPROM | LIZE |
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