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PDF STA2500D Data sheet ( Hoja de datos )
| Número de pieza | STA2500D | |
| Descripción | Wireless Communication & Connectivity ICs | |
| Fabricantes | ST Microelectronics | |
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STA2500D
Bluetooth™ V2.1 + EDR ("Lisbon") for automotive applications
Features
■ Based on Ericsson technology licensing
baseband core (EBC)
■ Bluetooth™ specification compliance:
V2.1 + EDR (“Lisbon”)
– Point-to-point, point-to-multipoint (up to 7
slaves) and scatternet capability
– Support ACL and SCO links
– Extended SCO (eSCO) links
– Faster connection
■ HW support for packet types
– ACL: DM1, DM3, DM5, DH1, DH3, DH5, 2-
DH1, 2-DH3, 2-DH5, 3-DH1, 3-DH3, 3-DH5
– SCO: HV1, HV3 and DV
– eSCO: EV3, EV4, EV5, 2-EV3, 2-EV5, 3-
EV3, 3-EV5
■ Adaptive frequency hopping (AFH)
■ Channel quality driven data rate (CQDDR)
■ “Lisbon” features
– Encryption pause/resume (EPR)
– Extended inquiry response (EIR)
– Link supervision time out (LSTO)
– Secure simple pairing
– Sniff subrating
– Quality of service (QoS)
Packet boundary flag
Erroneous data delivery
■ Transmit power
– Power class 2 and power class 1.5 (above
4 dBm)
– Programmable output power
– Power class 1 compatible
■ HCI
– HCI H4 and enhanced H4 transport layer
– HCI proprietary commands (e.g.
peripherals control)
– Single HCI command for patch/upgrade
download
– eSCO over HCI supported
■ Supports pitch-period error concealment (PPEC)
■ Efficient and flexible support for WLAN
coexistence scenarios
LFBGA48 (6x6x1.4mm; 0.8mm Pitch)
■ Low power consumption
– Ultra low power architecture with 3 different
low-power levels
– Deep sleep modes, including host-power
saving feature
– Dual wake-up mechanism: initiated by the
host or by the Bluetooth device
■ Communication interfaces
– Fast UART up to 4 MHz
– Flexible SPI interface up to 13 MHz
– PCM interface
– Up to 10 additional flexibly programmable
GPIOs
– External interrupts possible through the
GPIOs
– Fast I2C interface as master
■ Clock support
– System clock input (digital or sine wave) at
9.6, 10, 13, 16, 16.8, 19.2, 26, 33.6 or 38.4 MHz
– Low power clock input at 3.2 kHz, 32 kHz
and 32.768 kHz
■ ARM7TDMI CPU
■ Memory organization
– On chip RAM, including provision for
patches
– On chip ROM, preloaded with SW up to
HCI
■ Ciphering support up to 128-bit key
■ Single power supply with internal regulators for
core voltage generation
■ Supports 1.65 V to 2.85 V I/O systems
■ Auto calibration (VCO, filters)
Table 1. Device summary
Order code
Package
Packing
STA2500D
STA2500DTR
LFBGA48
Tray
Tape and reel
July 2009
Doc ID 16067 Rev 1
1/57
www.st.com
1
1 page  
www.DataSShTeeAt42U5.0co0mD
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Block diagram and electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pinout (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Active high clock request input and output combined with UART or SPI . . . . . . . . . . . . . . 28
Active low clock request input and output combined with UART . . . . . . . . . . . . . . . . . . . . 28
Active low clock request input and output combined with SPI . . . . . . . . . . . . . . . . . . . . . . 28
Deep sleep mode entry and wake-up through H4 UART . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Entering deep sleep mode through enhanced H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Wake-up by the host through enhanced H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Wake-up by the Bluetooth controller with data transmission to the host,
through enhanced H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Deep sleep mode entry and wake-up through H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Entering deep sleep mode, pending data on UART interface, through UART
with handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Wakeup by host through UART with handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PTA diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Bluetooth master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SPI data transfer timing for data length of 8 bits and lsb first, full duplex . . . . . . . . . . . . . . 42
SPI setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
PCM (A-law, µ-law) standard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Linear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Multislot operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PCM interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LFBGA48 (6x6x1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . . . . 50
Package markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Doc ID 16067 Rev 1
5/57
5 Page 
www.DataSShTeeAt42U5.0co0mD
Quick reference data
Table 12. Current consumption(1) (continued)
State
Typ. Unit
Active: data (DH5) Master or Slave
(723.2 kbps asymmetrical in TX mode)
(433.9 kbps symmetrical)
35.4 mA
35.4 mA
Active: data (2-DH5) Master or Slave (869.7 kbps symmetrical)
35.4 mA
Active: data (3-DH5) Master or Slave (1306.9 kbps symmetrical)
35.4 mA
Active: audio eSCO (EV3), (64 kbps symmetrical TeSCO = 6)
Master mode
Slave mode
12 mA
15 mA
Active: audio eSCO (2-EV3), (64 kbps symmetrical TeSCO = 12)
Master mode
Slave mode
7.8 mA
11.7 mA
Active: audio eSCO (3-EV3), (64 kbps symmetrical TeSCO = 18)
Master mode
Slave mode
6.5 mA
10.5 mA
Active: audio eSCO (EV5), (64 kbps symmetrical TeSCO = 36), Master mode
8 mA
Active: audio eSCO (EV5), (64 kbps symmetrical TeSCO = 36), Slave mode
11.9 mA
Active: audio eSCO (2-EV5), (64 kbps symmetrical TeSCO = 36), Master mode
6.3 mA
Active: audio eSCO (3-EV5), (64 kbps symmetrical TeSCO = 36), Master mode
5.75 mA
1. The power consumption (except for power safe modes i.e. complete power down and deep sleep mode)
will rise (with approx. 200 µA) if an analog system clock is used instead of a digital clock.
2. In functional sleep mode, the baseband clock is still running.
Doc ID 16067 Rev 1
11/57
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STA2500D.PDF ] | |
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