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PDF ICS663 Data sheet ( Hoja de datos )
| Número de pieza | ICS663 | |
| Descripción | PLL BUILDING BLOCK | |
| Fabricantes | Integrated Circuit Systems | |
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ICS663
PLL BUILDING BLOCK
Description
The ICS663 is a low cost Phase-Locked Loop (PLL)
www.dadtaesshiegent4eud.cfoomr clock synthesis and synchronization.
Included on the chip are the phase detector, charge
pump, Voltage Controlled Oscillator (VCO) and an
output buffer. Through the use of external reference
and VCO dividers (implemented with the ICS674-01,
for example), the user can easily configure the device
to lock to a wide variety of input frequencies.
The phase detector and VCO functions of the device
can also be used independently. This enables the
configuration of other PLL circuits. For example, the
ICS663 phase detector can be used to control a VCXO
circuit such as the MK3754.
For applications requiring Power Down or Output
Enable features, please refer to the ICS673-01.
Features
• Packaged in 8-pin SOIC
• Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz
to 120 MHz (5 V)
• External PLL loop filter enables configuration for a
wide range of input frequencies
• Ability to accept an input clock in the kHz range
(video Hsync, for example)
• 25 mA output drive capability at TTL levels
• Lower power CMOS process
• +3.3 V ±5% or +5 V ±10% operating voltage
• Used along with the ICS674-01, forms a complete
PLL circuit
• Phase detector and VCO blocks can be used
independently for other PLL configurations
• Industrial temperature version available
• For better jitter performance, use the MK1575
Block Diagram
Clock Input
REFIN
FBIN
LF LFR
VDD
Phase/
Frequency
Detector
Icp
UP
DOWN
VCO
Icp
1
MUX
40
2
SEL
External Feedback Divider
(such as the ICS674-01)
CLK
MDS 663 D
1
Revision 062904
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
1 page  
ICS663
PLL BUILDING BLOCK
External Components
Avoiding PLL Lockup
The ICS663 requires a minimum number of external
components for proper operation. A decoupling
capacitor of 0.01µF should be connected between VDD
www.daatansdheGeNt4uD.caosm close to the ICS663 as possible. A series
termination resistor of 33Ω may be used at the clock
output.
Special considerations must be made in choosing loop
components C1 and C2:
1) The loop capacitors should be a low-leakage type to
avoid leakage-induced phase noise. For this reason,
DO NOT use any type of polarized or electrolytic
capacitors.
2) Microphonics (mechanical board vibration) can also
induce output phase noise when the loop bandwidth is
less than 1 kHz. For this reason, ceramic capacitors
should have C0G or NP0 dielectric. Avoid high-K
dielectrics like Z5U and X7R. These and some other
ceramics have piezoelectric properties that convert
mechanical vibration into voltage noise that interferes
with VCXO operation.
For larger loop capacitor values such as 0.1µF or 1µF,
PPS film types made by Panasonic, or metal poly types
made by Murata or Cornell Dubilier are recommended.
For questions or changes regarding loop filter
characteristics, please contact your sales area FAE, or
ICS Applications.
In some applications, the ICS663 can “lock up” at the
maximum VCO frequency. The way to avoid this
problem is to use an external divider that always
operates correctly regardless of the CLK output
frequency. The CLK output frequency may be up to 2x
the maximum Output Clock Frequency listed in the AC
Electrical Characteristics above when the device is in
an unlocked condition. Make sure that the external
divider can operate up to this frequency.
Explanation of Operation
The ICS663 is a PLL building block circuit that includes
an integrated VCO with a wide operating range. The
device uses external PLL loop filter components which
through proper configuration allow for low input clock
reference frequencies, such as a 15.7 kHz Hsync input.
The phase/frequency detector compares the falling
edges of the clocks inputted to FBIN and REFIN. It then
generates an error signal to the charge pump, which
produces a charge proportional to this error. The
external loop filter integrates this charge, producing a
voltage that then controls the frequency of the VCO.
This process continues until the edges of FBIN are
aligned with the edges of the REFIN clock, at which
point the output frequency will be locked to the input
frequency.
Figure 1. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference
0.01µ F
200 kHz
+3.3 or 5 V
C2
VDD SEL
RZ C1
LF LFR
REFIN
FBIN
IC S 6 6 3
CLK
GND
20 MHz
200 kHz
100
Digital Divider such as
ICS674-01
MDS 663 D
5
Revision 062904
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet ICS663.PDF ] | |
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