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Zarlink Semiconductor |
ZL30112
SLIC/CODEC DPLL
Data Sheet
Features
• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or
www.datas1he9e.4t44u.cMomHz input
• Provides 2.048 MHz and 8.192 MHz output clocks
and an 8 kHz framing pulse
• Automatic entry and exit from freerun mode on
reference fail
• Provides DPLL lock and reference fail indication
• DPLL bandwidth of 29 Hz for all rates of input
references
• Less than 0.6 nsecpp intrinsic jitter on all output
clocks
• 20 MHz external master clock source: clock
oscillator or crystal
• Simple hardware control interface
November 2007
Ordering Information
ZL30112LDE1
32 Pin QFN* Tubes, Bake
& Drypack
*Pb Free Matte Tin
-40°C to +85°C
Applications
• Synchronizer for POTS SLIC/CODEC
• Rate convert NTR 8 kHz or GPON physical
interface clock to TDM clock
Description
The ZL30112 SLIC/CODEC DPLL contains a digital
phase-locked loop (DPLL), which provides timing and
synchronization for SLIC/CODEC devices.
The ZL30112 generates TDM clock and framing
signals that are phase locked to the input reference.
It helps ensure system reliability by monitoring its
reference for stability and by maintaining stable
output clocks during short periods when the
reference is unavailable.
REF
RST
OSCi
OSCo
Reference
Monitor
State Machine
Master
Clock
REF_FAIL
LOCK
DPLL
Mode
Control
C2o
C8o
F8ko
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved.
1.0 Physical Description
1.1 Pin Connections
www.datasheet4u.com
ZL30112
AGND
F8ko
REF
IC
IC
IC
VDD
IC
24 22
20 18
ZL30112 16
26
14
28
12
30
33 IC (E-pad)
32
2
46
10
8
GND
AVDD
VDD
IC
OSCi
OSCo
RST
IC
Data Sheet
Figure 2 - Pin Connections (32 pin 5 mm X 5 mm QFN)
2
Zarlink Semiconductor Inc.
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