|
Sanyo Semicon Device |
Ordering number : EN*5129A
CMOS LSI
LE28C1001M, T-90/12/15
Preliminary
1MEG (131072 words × 8 bits) Flash Memory
Overview
The LE28C1001M, T series ICs are 1 MEG flash memory
products that feature a 131072-word × 8-bit organization
and 5 V single-voltage power supply operation. CMOS
peripheral circuits are adopted for high speed, low power
dissipation, and ease of use. A 128-byte page rewrite
function provides rapid data rewriting.
Features
• Highly reliable 2-layer polysilicon CMOS flash
EEPROM process
• Read and write operations using a 5 V single-voltage
power supply
• Fast access time: 90, 120, and 150 ns
• Low power dissipation
— Operating current (read): 30 mA (maximum)
— Standby current:
20 µA (maximum)
• Highly reliable read/write
— Erase/write cycles:
104/103 cycles
— Data retention:
10 years
• Address and data latches
• Fast page rewrite operation
— 128 bytes per page
— Byte/page rewrite time: 5 ms (typical)
— Chip rewrite time:
5 s (typical)
• Automatic rewriting using internally generated Vpp
• Rewrite complete detection function
— Toggle bit
— Data polling
• Hardware and software data protection functions
• All inputs and outputs are TTL compatible.
• Pin assignment conforms to the JEDEC byte-wide
EEPROM standard.
• Package
SOP 32-pin (525 mil) plastic package : LE28C1001M
TSOP 32-pin (8 × 20 mm)plastic package : LE28C1001T
Package Dimensions
unit: mm
3205-SOP32
[LE28C1001M]
unit: mm
3224-TSOP32
[LE28C1001T]
SANYO: SOP32
SANYO: TSOP32 (TYPE-I)
These FLASH MEMORY products incorporate technology licensed Silicon Storage Technology, Inc.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
D3096HA (OT)/N3095HA (OT) No. 5129-1/14
Block Diagram
LE28C1001M, T-90/12/15
Pin Assignments
Pin Functions
Symbol
A16 to A0
Pin
Address input
DQ7 to DQ0 Data input and output
CE
OE
WE
VCC
VSS
N.C.
Chip enable
Output enable
Write enable
Power supply
Ground
No connection
A05759
Function
Supply the memory address to these pins.
The address is latched internally during a write cycle.
These pins output data during a read cycle and input data during a write cycle.
Data is latched internally during a write cycle.
Outputs go to the high-impedance state when either OE or CE is high.
The device is active when CE is low.
When CE is high, the device becomes unselected and goes to the standby state.
Makes the data output buffers active.
OE is an active-low input.
Makes the write operation active.
WE is an active-low input.
Apply 5 V (±10%) to this pin.
These pins must be left open.
A05760
No. 5129-2/14
|