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PDF CP1181 Data sheet ( Hoja de datos )
| Número de pieza | CP1181 | |
| Descripción | 21 ch E1/T1 Mapper | |
| Fabricantes | CHIP | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CP1181 (archivo pdf) en la parte inferior de esta página. Total 3 Páginas | ||
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21 Channel E1/T1 Mapper
Product Brief
CP1181
OPTRANS Series
CP1181_PB_Rev1.0 March, 2005
www.daOtasVheEet4Ru.cVomIEW
The CP1181 is one of the OPTRANS series chips designed by Chiphomer
Technology Limited. It is designed for add/drop multiplexer, terminal
multiplexer, dual and single unidirectional ring applications. 21 E1/T1
signals are mapped to and from asynchronous TU12. The CP1181 interfaces
to a byte-wide 19.44 MHz Telecom Bus.
FEATURES
Asynchronously mapping/de-mapping 21 E1 or T1 traffics into/from
STM-1. T1 traffic mapping path is T1 VC11 TU12.
Configurable receive and transmit TU12 time-slots via microprocessor
Detects loss of input clock on Telecom Bus
TEBGA256
-40 ~ 85℃
Interprets TU12 pointer according to G.783 (2000/10) and G.707 (2000/10)
Detects LOM, TU-LOP and TU-AIS alarms
Detects Remote Defect Indication (RDI), Remote Error Indication (REI), RFI alarm and Path Label Mismatch
(PLM) alarm
Provides 12-bit performance counters for BIP-2 errors and 11-bit performance counters for tributary REI errors
Detects degraded signals(DEG) and Excessive Error defects (EXC) based on received BIP-2 errors.
Extracts the 16-byte J2 sequence into microprocessor accessible registers, and checks the J2 sequence to detect
TIM alarm
Detects the K4 (bit5-bit7) and V5 bit8 for Enhanced Defect Indicator (E-RDI)
Captures filtered K4 byte into microprocessor accessible registers
Extracts V5 and K4 bytes into microprocessor accessible registers
Extracts N2 byte and O bits into microprocessor accessible registers
RTCLKA
RTPLA
RTMFA
RTJ0J1V1A
RTDA[7:0]
RTPARA
RTINDA
RTCLKB
RTPLB
RTMFB
RTJ0J1V1B
RTDB[7:0]
RTPARB
RTINDB
TTCLKA
TTPLA
TTMFA
TTJ0J1V1A
TTDA[7:0]
TTPARA
TTINDA
TTCLKB
TTPLB
TTJ0J1V1B
TTMFB
TTDB[7:0]
TTPARB
TTINDB
Pointer
Interpreter A
POH
Terminate A
Pointer
Interpreter B
POH
Terminate B
DPLL
Mux Desync
Switching
Control
PRBS
Analyzer
Mux
Mux
Pointer
Generator A
POH Build A
Pointer
Generator B
POH Build B
Sync
Mux
Mux
PRBS
Generator
Microprocessor Interface
E1_TDATA[0..20]/
T1_DATA[0..20]
E1_TCLK[0..20]/
T1_TCLK[0..20]
E1_RDATA[0..20]/
T1_RDATA[0..20]
E1_RCLK[0..20]/
T1_RCLK[0..20]
Copyright ©2005 Chiphomer Technology Limited
Page 1 of 1
1 page | ||
| Páginas | Total 3 Páginas | |
| PDF Descargar | [ Datasheet CP1181.PDF ] | |
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