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PDF MV3100 Data sheet ( Hoja de datos )

Número de pieza MV3100
Descripción 3V Codec
Fabricantes Zarlink Semiconductor 
Logotipo Zarlink Semiconductor Logotipo



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No Preview Available ! MV3100 Hoja de datos, Descripción, Manual

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THIS DOCUMENT IS FOR MAINTENANCE
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RECOMMENDED FOR NEW DESIGNS

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MV3100 pdf
MV3100
FS
tSR
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BCLK
tSSU tSH
tDZH
tDZL
tSF
tDLH
tDHL
TXOUT
MSB
tRSU
RXIN
MSB
tRH
tDHZ
tDLZ
LSB
LSB
Parameter
FS to BCLK set-up time
FS to BCLK hold time
BCLK to FS rising time
FS falling to BCLK time
Output delay from Z to high
Output delay from Z to low
Output delay from high to Z
Output delay from low to Z
Output delay from high to low
Output delay from low to high
RXIN set-up time
RXIN hold time
NOTE 2. Not production tested
Fig. 4 PCM Interface timing diagram (expanded)
Value
Symbol
Units
Min. Typ. Max.
tSSU
tSH
tSR
tSF
tDZH
tDZL
tDHZ
tDLZ
tDHL
tDLH
tRSU
tRH
10
15
25
25
10
15
ns
ns
ns
ns
25 ns
25 ns
25 ns
25 ns
30 ns
30 ns
ns
ns
Table 3 PCM Interface timings (see Fig. 4)
Conditions
Notes
2
2
2
2
2
2
2
2
2
2
codes can be found in CCITT G711.
In both codes positive values are represented by a sign bit of
1. The A-Law data is alternate digit inverted (ADI) and the µ-Law
magnitude data is in effect inverted. These techniques are used
to ensure that there are sufficient data transitions for good clock
recovery (not performed by the MV3100) on the Received side
of the digital trunk lines when the channel is quiet.
CONTROL INTERFACE (SEE FIGS. 5 AND 6))
The Control Interface essentially has two sections. Firstly the
serial/parallel input shift and address decode section, which
controls the control registers. This is the Control Interface proper.
Secondly, the reset section which generates a digital chip reset
from the combination of ‘hard’ (i.e., power-on/pin generated)
and ‘soft’ (i.e., programmed into the control registers) resets.
The data is serially clocked into the DATA input by the
CLOCK input. The first 5 bits are the data to be stored and the
second 3 bits identify which register is to be addressed. After the
data has been clocked in, a separate ENABLE pulse stores the
data in the appropriate register.
The Control Interface has four inputs:
CLOCK
Control Interface clock
DATA
Serial data input for the control registers
ENABLE Control Interface enable Signal
RESET
See below
The RESET input is used to provide a full chip reset. The
general rule is that, on reset, the chip is set to handset
operation, minimum gain settings and all parts powered
down, with the exception of the PLL and the VREF (CR0<1>)
which is powered up.
CLOCK
tDSU
DATA XX D0
D1
ENABLE
LATCHED
DATA
tDH
D2 D3
D4
tCE1
tCE2
A0 A1
A2 XXXXXXXXXXXXXXXXXXXXXXXXXXXX
tENW
PREVIOUS DATA
tPED
Fig. 5 Control Interface timing diagram
NEW DATA
4

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MV3100 arduino
MV3100
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TRANSMIT OUT-OF-BAND SIGNAL
Response relative to 1kHz. Input signal level = 234·8dBV.
Output is total power relative to that for 1kHz.
Frequency (Hz) Min. (dB) Typ. (dB) Max. (dB)
4650
5000
6000
6500
7000
7500
Table 19
230
231·5
235
236
237·5
239
RECEIVE CHARACTERISTICS
Receive gain = nominal (see Table 21)
Characteristic
Value
Symbol
Min. Typ. Max.
Units
Conditions
Notes
Gain (RXIN to LSOPP/LSOPN)
AVRX
26·1
dBV/dBm0 1kHz
Gain (AUXIN to LSOPP/LSOPN)
AVRA
13·4
dB 1kHz
Gain variation with temperature
AVTR 21·0
11·0 dB 230°C to 170°C
18
Gain variation with supply
Clipping level distortion
Wide band noise
Narrow band noise
Signal out-of-band noise
AUXIN input impedance
Sampling noise
Power supply rejection ratio
AVSR
DCLR
NWBR
NNBR
NOBR
ZINA
NS
PSRR
20·5
45
26
10·5
,0·5
272
276
20
279
dB
%
dBVp
dB
dB
k
dBV
dB
2·7V to 5·5V
3dBm0, 1kHz
At 8kHz
18
19
18, 20
21
18, 22
Louspeaker output load
ZL
88 105
nF
Table 20
NOTES
18. Not production tested.
19. Bandwidth 300Hz to 3400Hz psophometrically weighted.
20. Any 10Hz band centred over the frequency range 305Hz to 3395Hz.
21. For an input signal of 0dBm0 at 1kHz, the ratio between the signal at 1kHz and any signal between 4kHz and 8kHz at the loudspeaker.
22. 20mVp-p sinewave at 500Hz applied to the positive supply.
10

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