파트넘버.co.kr KS1461 데이터시트 PDF


KS1461 반도체 회로 부품 판매점

RF Signal Processor



Samsung Semiconductor 로고
Samsung Semiconductor
KS1461 데이터시트, 핀배열, 회로
PRELIMINARY
RF SIGNAL PROCESSOR
KS1461
INTRODUCTION
The KS1461 receives optical signals from the optical pickup and makes the data-generation RF
(Radio Frequency) signals needed in the system part, and the servo error signal and monitor signals, needed for
stable servo control. The modes to which this RF IC can be applied are the CD 1×, 2×, 4×, and 8× modes
(Wide PLL +/- 20%) and the DVD 1× and 2× CLV (Constant Linear Velocity) modes.
FEATURES
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• Compatible to play back of CDs at 1×, 2×, 4×, or 8×, and DVDs at 1× and 2×
• Can deal with all of CD-R corresponding P/Us’ optical signal input without additional circuits
• Built-in PreAmp that correspond to various P/U unit and gain controllable
• Built-in AGC (Automatic Gain Control) circuit for intensity radiation detection feedback
• RF AMP & equalizer for CD 1×, 2×, 4×, 8× and DVD 1×, and 2× compatibility
• Astigmatism FE (Focus Error) AMP for CD and DVD built-in
• TE (Tracking Error) AMP built-in for 3-beam method of CD
• TE (Tracking Error) AMP built-in to the 1-beam DPD (Differential Phase Detector) for DVD
• RF mirror detection circuit built-in for CD and DVD
• RF defect detection circuit built-in for CD and DVD
• FOK (Focus O.K) signal detection circuit built-in for CD and DVD
• Built-in RF envelope signal generator circuit for CD and DVD
• Built-in ALPC (Automatic Laser Power Control) circuit for CD and DVD
• Built-in standard voltage generating circuit for analog circuit
• Built-in detection circuit for abnormal wave forms
• Built-in Auto Offset compensation circuit
• Range of power in operation: 4.5 ~ 5.5V
• 100 PIN, TQFP (0.5 mm PITCH)
1


KS1461 데이터시트, 핀배열, 회로
KS1461
BLOCK DIAGRAM
PRELIMINARY
RF SIGNAL PROCESSOR
100 99 98 97 96 95 94 93 92 91 90 89 88 87
86 85 84 83 82 81 80 79 78 77 76
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t o RF EQ
TUNI NG BLOCK
AGC-HOLD(00 H)
AGC_ D ET
ACD
BCD
CCD
DCD
1
2
3
4
ADVD
BDVD
CDVD
DDVD
5
6
7
8
RF
MUX
A
B
C
D
MUX
+
+ RF SUM
+ & AGC
+
GAIN_ EQ(02 H)
RF
Equalizer
RF RP
CDRSEL(00 H )
RREFBF 9
RREFEQ
10
VREF
GENERATOR
RREF 11
DELAY_AB(07 H )
DELAY_C D(07 H)
PLL CTL
g a_ R FSUM(08 H )
DVCTL_SE L(02H)
D+
GCA
+EQ
D
MUX3
D+
GCA
EQ
D+
GA_PLL DN (09 H)
GA_PLL DP(09 H )
VREFEQ 12
E 13
F 14
EQ VC
AMP
GAIN_ TE3(02 H )
GCA
-
T E3B
GCA
+
O F ST HO LD
TEOFST(04 H )
TBAL(01 H)
DPDEQ1
CD1 S12
T E1R ES
DELAY _SE L(00H)
PLLCTL
TBA L(01H)
RFCT
&
MIRR
HOL D_CTL( 0 8 H)
D PD MU TE
D PD _MU TE( 02H)
SEOFHOLD
FLT_CTL(00H)
C AL _ EN D B( 0 2 H)
COM
COM
DPDEQ2
DELAY PD,LPF
TEOFST( 0 4 H)
PDL IMITRES
TE1_LIMIT
PD_LIMI T(08H)
Ab normal waveform FAUL TOUT
Detectio n circu it
DELAY _SE L(00H)
PLLCTL
ADVD1 15
BDVD1 16
CDVD1 17
DDVD1 18
ACD1 19
BCD1 20
CCD1 21
DCD1 22
D1
B1
SUB
C1
A1
RF
MUXGAIN_FE(03 H)
FE_OFST(05 H )
FE
CDR SEL(00 H)
GAIN_ ABCD(00 H )
+
+ ABCD
+ SUM
+
-
EQIN
ENV_SEL(02 H)
O F ST HO LD
ABCD_ OFST(06 H )
MUX
AVCC 23
VREFA 24
FOFST 25
CDRSEL(00 H )
ANALOG
VC AMP
LDONB(00 H)
ALPC
+
-
FOFST
MUX
TESEL(00 H )
-+
ENVELOPE
FOK
BCA
BLOCK
BCA
CD1
S12
DVD1
DVD2
LD ON B
FLT_CTL
CDRSE L
TES E L
AGCHOLD
TBAL
GAI N_TE 3
ENV_SE L
DVCTL_SE L
DPD_MUTE
GAI N_EQ
GAI N_FE
GAI N_ABCD
TE_OFST
FE_OFST
ABCD_OFST
DELAY _CD
DELAY _AB
PDLIM I T
ga_RFSU M
H OLD _CTL
ga_PLLD P
ga_PLLD N
AUTO
O F ST CT L
S/IF
BLOCK
DPD
VC AMP
to DPD
B L OCK
DEFECT
75 BCAO
74 BCAI
73 RESET
72 OSC
71 STB
70 CLOCK
69 DATA
68 RREFDLY
67 VREFDPD
66 DPDGND
65 TE1RES
64 PLLCTL
63 DPDMUTE
62 FAULTOUT
61 DPDEQ 2
60 DPDEQ 1
59 TE3OFST
58 BCA
57 MIRR
56 DPDVCC
55 DFCT2
54 DFCT1
53 DFCTTH1
52 DFCTTH2
51 DVCC
26
27 28 29 30 31 32 33 34 35 36
37 38 39 40 41 42 43 44 45 46 47 48 49 50
LDI-97-P002-R2
2 98-02-10




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KS1461

RF Signal Processor - Samsung Semiconductor