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R8A66171SP 반도체 회로 부품 판매점

A2RT



Renesas Technology 로고
Renesas Technology
R8A66171SP 데이터시트, 핀배열, 회로
R8A66171DD/SP
A2RT (ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER)
REJ03F0269-0100
Rev. 1.00
Feb.19.2008
DESCRIPTION
The R8A66171 is an integrated circuit for asynchronous serial data communications. It is used in combina-
tion with an 8-bit microprocessor and is produced using the silicon gate CMOS technology. R8A66171 is
the succession product of M66230.
FEATURES
Baud rate generator
4-byte FIFO data buffer for transmission and reception
www.DataSheet4UE.crormor detection : CRC-CCITT
Wakeup function
Majority-voting system by sampling three points of received data
Transmission / reception data format ( number of bits )
Start bit 1
Data bit 8
Wakeup bit 1 or nil
Parity bit 1 or nil
Stop bit 1 or 2
Transmission speed
500Kbps (max)
Access time
ta (/RD-D) : 100ns
High output current
IOH=-24mA IOL=24mA TxD, /RTS, P0, P1 pins
Schmitt triggered input RxD, /CTS, /RESET pins
Wide operating supply voltage range (Vcc=3.0~3.6V or Vcc=4.5~5.5V)
Wide operating temperature range (Ta=-40~85OC)
APPLICATION
Data communication control that uses microprocessor
PIN CONFIGURATION (TOP VIEW)
D0
D1
DATA BUS
D2
D3
D4
D5
D6
D7
READ CONTROL INPUT RD
WRITE CONTROL INPUT WR
COMMAND/DATA C/D
CONTROL INPUT GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 TxD TRANSMISSION DATA OUTPUT
22 RxD RECEPTION DATA INPUT
21 CTS CLEAR-TO-SEND INPUT
20 RTS REQUEST-TO-SEND OUTPUT
19 P0
PORT OUTPUT
18 P1
17 INT INTERRUPT OUTPUT
16 CS CHIP SELECT INPUT
15 RESET RESET INPUT
14 X1 CLOCK INPUT
13 X2 CLOCK OUTPUT
REJ03F269-0100 Rev.1.00 Feb.19.2008
Page 1 of 22


R8A66171SP 데이터시트, 핀배열, 회로
R8A66171DD/SP
FUNCTION
The R8A66171 is a UART (Universal Asynchronous Receiver/Transmitter) and is used in the peripheral
circuit of a MCU. The R8A66171 receives parallel data, converts into serial format, and then transmits the
serial data via the TxD pin. The device also receives data via the RxD pin from external circuits and converts
it into parallel format, and sends the parallel data via the data bus.
BLOCK DIAGRAM
Reset input
Command/Data control
input
www.DataSheet4U.com Read control input
Write control input
Chip select input
RESET 15
C/D 11
RD 9
WR 10
CS 16
Data bus
D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
Clock input
Clock output
X1 14
X2 13
READ/
W RITE
CONTRO
L
CIRCUIT
8
DATA
BUS 8
BUFFER
TRANSMIT DATA BUFFER
4-BYTE FIFO
8
TRANSMIT
BUFFER
TRANSMIT CONTROL, ERROR DETECTION CODE
GENERATION(CRC) CIRCUIT
8 COMMAND
REGISTER
8
STATUS REGISTER
RECEIVE CONTROL, ERROR DETECTION(CRC) CIRCUIT
8
RECEIVE DATA BUFFER
4-BYTE FIFO
RECEIVE
BUFFER
BAUD RATE
GENERATOR
SAMPLING CLOCK
1/16 DIVISION
CIRCUIT
TRANSFER
CLOCK
24 VCC
12 GND
23 TXD Transmission data
output
Clear-to-send
21 CTS input
Request-to-send
20 RTS output
22 RXD
19 P0
18 P1
17 INT
Reception data
input
Port output
Interrupt output
REJ03F269-0100 Rev.1.00 Feb.19.2008
Page 2 of 22




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