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PDF TMP1941AF Data sheet ( Hoja de datos )
| Número de pieza | TMP1941AF | |
| Descripción | 32-Bit TX System RISC | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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32-Bit TX System RISC
TX19 Family
TMP1941AF
1 page  
Contents
TMP1941AF
Handling Precaution
TMP1941AF
1. Features ................................................................................................................................................................... 1
2. Signal Descriptions ................................................................................................................................................. 5
2.1 Pin Assignment .................................................................................................................................................. 5
2.2 Pin Usage Information ....................................................................................................................................... 6
www.DataSheet34.U.comCore Processor ........................................................................................................................................................ 9
3.1 Reset Operation ................................................................................................................................................. 9
4. Memory Map......................................................................................................................................................... 10
5. Clock/Standby Control .......................................................................................................................................... 11
5.1 Clock Generation............................................................................................................................................. 12
5.1.1 Main System Clock ................................................................................................................................. 12
5.1.2 Subsystem Clock..................................................................................................................................... 12
5.1.3 Clock Source Block Diagrams ................................................................................................................ 13
5.2 Clock Generator (CG) Registers...................................................................................................................... 14
5.2.1 System Clock Control Registers.............................................................................................................. 14
5.2.2 ADC Conversion Clock .......................................................................................................................... 16
5.2.3 STOP/SLEEP Wake-up Interrupt Control Registers (INTCG Registers) ............................................... 16
5.2.4 Interrupt Request Clear Register ............................................................................................................. 18
5.3 System Clock Control Section ......................................................................................................................... 19
5.3.1 Oscillation Stabilization Time When Switching Between NORMAL and SLOW Modes...................... 19
5.3.2 System Clock Output .............................................................................................................................. 20
5.3.3 Reducing the Oscillator Clock Drive Capability..................................................................................... 20
5.4 Prescalar Clock Control Section ...................................................................................................................... 21
5.5 Clock Frequency Multiplication Section (PLL)............................................................................................... 21
5.6 Standby Control Section .................................................................................................................................. 22
5.6.1 TMP1941AF Operation in NORMAL and Standby Modes.................................................................... 23
5.6.2 CG Operation in NORMAL and Standby Modes ................................................................................... 23
5.6.3 Processor and Peripheral Block Operation in Standby Modes................................................................ 23
5.6.4 Wake-up Signaling.................................................................................................................................. 24
5.6.5 STOP Mode ............................................................................................................................................ 26
5.6.6 Returning from a Standby Mode............................................................................................................. 26
6. Interrupts ............................................................................................................................................................... 29
6.1 Overview ......................................................................................................................................................... 29
6.2 Interrupt Sources.............................................................................................................................................. 31
6.3 Interrupt Detection........................................................................................................................................... 33
6.4 Resolving Interrupt Priority ............................................................................................................................. 33
6.5 Register Description ........................................................................................................................................ 34
6.5.1 Interrupt Vector Register (IVR) .............................................................................................................. 34
6.5.2 Interrupt Mode Control Registers (IMCF–IMC0) .................................................................................. 35
6.5.3 Interrupt Request Clear Register (INTCLR) ........................................................................................... 35
7. I/O Ports ................................................................................................................................................................ 36
7.1 Address/Data Bus Bits 0–7 (AD0–AD7)......................................................................................................... 40
7.2 Address/Data Bus Bits 8–15 (AD8–AD15) / Address Bus Bits 8–15 (A8–A15) ............................................ 40
7.3 Address Bus Bits 16–23 (A16–A23) ............................................................................................................... 41
7.4 RD , WR , HWR , WAIT , BUSRQ , BUSAK , R /W ..................................................................................... 41
7.5 Port 37 ............................................................................................................................................................. 43
7.6 Port 4 (P40–P44) ............................................................................................................................................. 44
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5 Page 
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Handling Precautions
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet TMP1941AF.PDF ] | |
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