파트넘버.co.kr T2316162A 데이터시트 PDF


T2316162A 반도체 회로 부품 판매점

1024K x 16 DYNAMIC RAM EDO PAGE MODE



Taiwan Memory Technology 로고
Taiwan Memory Technology
T2316162A 데이터시트, 핀배열, 회로
tm TE
CH
DRAM
T2316162A
1024K x 16 DYNAMIC RAM
EDO PAGE MODE
FEATURES
Industry-standard x 16 pinouts and timing
functions.
Single 5V (±10%) power supply.
www.DataSheet4U.com
All device pins are TTL- compatible.
1K-cycle refresh in 16ms.
Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
Extended data-out (EDO) PAGE MODE access
cycle.
BYTE WRITE and BYTE READ access cycles.
OPTION
TIMING
MARKING
45ns -45
50ns -50
60ns -60
PACKAGE
42-pin SOJ
J
44/50-pin TSOPII
S
PIN ASSIGNMENT ( Top View )
VDD
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 Vss
41 DQ15
40 DQ14
39 DQ13
38 DQ12
37 Vss
36 DQ11
35 DQ10
34 DQ9
33 DQ8
32 NC
31 CASL
30 CASH
29 OE
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 Vss
GENERAL DESCRIPTION
The T2316162A is a randomly accessed solid state
memory containing 16,777,216 bits organized in a
x16 configuration. The T2316162A has both
BYTE WRITE and WORD WRITE access cycles
via two CAS pins. It offers Fast Page mode with
Extended Data Output.
The T2316162A CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high
during WRITE will result in a BYTE WRITE.
CASL transiting low in a WRITE cycle will write
data into the lower byte (DQ0~DQ7), and CASH
transiting low will write data into the upper byte
(DQ8~DQ15).
VDD
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
NC
1
2
3
4
5
6
7
8
9
10
11
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
15
16
17
18
19
20
21
22
23
24
25
50 Vss
49 DQ15
48 DQ14
47 DQ13
46 DQ12
45 Vss
44 DQ11
43 DQ10
42 DQ9
41 DQ8
40 NC
36 NC
35 CASL
34 CASH
33 OE
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 Vss
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: APR. 2002
Revision:E


T2316162A 데이터시트, 핀배열, 회로
tm TE
CH
FUNCTIONAL BLOCK DIAGRAM
T2316162A
www.DataSheet4U.com
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
WE
CASL
CASH
CAS
NO.2 CLOCK
GENERATOR
COLUMN.
10 ADDRESS
BUFFER
REFRESH
CONTROLLER
REFRESH
COUNTER
10
ROW.
10 ADDRESS
BUFFERS(10)
RAS
NO.1 CLOCK
GENERATOR
CONTROL
LOGIC
DATA-IN BUFFER
10
COLUMN
DECODER
1024
16
SENSE AMPLIFIERS
I/O GATING
1024x 16
DATA-OUT
BUFFER
1
6
DQ0
.
16 .
DQ15
OE
1024x 1024 x 16
10
1024
MEMORY
ARRAY
Vcc
Vss
PIN DESCRIPTIONS
SYM.
A0-A9
RAS
CASH
CASL
WE
OE
DQ0 – DQ15
Vcc
Vss
NC
TYPE
Input
Input
Input
Input
Input
Input
Input/ Output
Supply
Ground
-
DESCRIPTION
Address Input
Row Address Strobe
Column Address Strobe /Upper Byte Control
Column Address Strobe /Lower Byte Control
Write Enable
Output Enable
Data Input/ Output
Power, 5V
Ground
No Connect
TM Technology Inc. reserves the right
P. 2
to change products or specifications without notice.
Publication Date: APR. 2002
Revision:E




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1024K x 16 DYNAMIC RAM EDO PAGE MODE - Taiwan Memory Technology