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PDF BC417143B-ES-IRN Data sheet ( Hoja de datos )

Número de pieza BC417143B-ES-IRN
Descripción Single Chip Bluetooth
Fabricantes Cambridge Silicon Radio　
Logotipo Cambridge Silicon Radio Logotipo



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No Preview Available ! BC417143B-ES-IRN Hoja de datos, Descripción, Manual

Device Features
_äìÉ`çêÉ»QJbñíÉêå~ä
ƒ Fully Qualified Bluetooth v1.2 system
ƒ Enhanced Data Rate (EDR) compliant with v0.9
of specification for both 2Mbps and 3Mbps
modulation modes
ƒ Full Speed Bluetooth Operation with Full
Piconet Support
www.DataSheet4U.cƒomScatternet Support
ƒ 1.8V core, 1.8 to 3.6V I/O
ƒ Low Power 1.8V Operation
ƒ Small footprint 8 x 8mm 96-ball VFBGA
Package
ƒ Also available in 6 x 6mm package option
ƒ Minimum External Components
ƒ Integrated 1.8V regulator
ƒ USB and Dual UART Ports
ƒ Support for 802.11 Coexistence
ƒ Support for 8Mbit External Flash
ƒ RoHS Compliant
General Description
_äìÉ`çêÉQJbñíÉêå~ä is a single chip radio and
baseband IC for Bluetooth 2.4GHz systems
including enhanced data rates (EDR) to 3Mbps.
BC417143B interfaces to 8Mbit of external Flash
memory. When used with the CSR Bluetooth
software stack, it provides a fully compliant
Bluetooth system to v1.2 of the specification for
data and voice communications.
RAM
External Memory
FLASH
SPI
RF IN
2.4
GHz
Radio
Baseband
DSP
I/O
UART/USB
RF OUT
MCU
PIO
PCM
Single Chip Bluetooth® v1.2 System
with EDR
Pre-Production Information Datasheet For
BC417143B-ES-IQN
BC417143B-ES-IRN
September 2004
Applications
ƒ PCs
ƒ Personal Digital Assistants (PDAs)
ƒ Computer Accessories (compact Flash Cards,
PCMCIA Cards, SD Cards and USB Dongles)
ƒ Access Points
ƒ Digital Cameras
BlueCore4-External has been designed to reduce the
number of external components required which ensures
production costs are minimised.
The device incorporates auto-calibration and built-in
self-test (BIST) routines to simplify development, type
approval and production test. All hardware and device
firmware is fully compliant with the Bluetooth v1.2
Specification (all mandatory and optional features).
To improve the performance of both Bluetooth and
802.11b/g co-located systems a wide range of
co-existence features are available including two types of
hardware signalling: basic activity signalling and Intel
WCS activity & channel signalling
XTAL
BlueCore4-External System Architecture
BC417143B-ds-001Pc
© Copyright Cambridge Silicon Radio 2004
Pre-Production Information
Page 1 of 107

1 page




BC417143B-ES-IRN pdf
Status Information
List of Figures
Figure 2.1: BlueCore4-External 8 x 8mm Device Pinout (BC417143B-ES-IQN) ..................................................... 9
Figure 3.1: BlueCore4-External 6 x 6mm Device Pinout (BC417143B-ES-IRN) ................................................... 15
Figure 7.1: BlueCore4-External Device Diagram .................................................................................................. 38
Figure 9.1: BlueCore HCI Stack ............................................................................................................................ 42
Figure 9.2: BlueCore RFCOMM Stack .................................................................................................................. 46
Figure 9.3: Virtual Machine ................................................................................................................................... 48
Figure 9.4: HID Stack............................................................................................................................................ 49
Figure 11.1: Circuit TX/RX_A and TX/RX_B ......................................................................................................... 53
Figure 11.2: Circuit RF_IN .................................................................................................................................... 54
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Figure 11.3: TCXO Clock Accuracy ...................................................................................................................... 55
Figure 11.4: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting......................................... 56
Figure 11.5: Crystal Driver Circuit ......................................................................................................................... 58
Figure 11.6: Crystal Equivalent Circuit .................................................................................................................. 58
Figure 11.7: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency............................. 61
Figure 11.8: Crystal Driver Transconductance vs. Driver Level Register Setting.................................................. 62
Figure 11.9: Crystal Driver Negative Resistance as a Function of Drive Level Setting ......................................... 63
Figure 11.10: Memory Write Cycle........................................................................................................................ 66
Figure 11.11: Memory Read Cycle........................................................................................................................ 67
Figure 11.12: Universal Asynchronous Receiver .................................................................................................. 68
Figure 11.13: Break Signal.................................................................................................................................... 69
Figure 11.14: UART Bypass Architecture ............................................................................................................. 70
Figure 11.15: USB Connections for Self Powered Mode ...................................................................................... 72
Figure 11.16: USB Connections for Bus Powered Mode ...................................................................................... 73
Figure 11.17: USB_DETACH and USB_WAKE_UP Signal .................................................................................. 74
Figure 11.18: Write Operation............................................................................................................................... 76
Figure 11.19: Read Operation............................................................................................................................... 76
Figure 11.20: BlueCore4-External as PCM Interface Master ................................................................................ 78
Figure 11.21: BlueCore4-External as PCM Interface Slave .................................................................................. 78
Figure 11.22: Long Frame Sync (Shown with 8-bit Companded Sample)............................................................. 79
Figure 11.23: Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 79
Figure 11.24: Multi Slot Operation with Two Slots and 8-bit Companded Samples .............................................. 80
Figure 11.25: GCI Interface................................................................................................................................... 80
Figure 11.26: 16-Bit Slot Length and Sample Formats ......................................................................................... 81
Figure 11.27: PCM Master Timing Long Frame Sync ........................................................................................... 83
Figure 11.28: PCM Master Timing Short Frame Sync........................................................................................... 83
Figure 11.29: PCM Slave Timing Long Frame Sync ............................................................................................. 85
Figure 11.30: PCM Slave Timing Short Frame Sync............................................................................................. 85
Figure 11.31: Example EEPROM Connection ...................................................................................................... 89
Figure 11.32: Example TXCO Enable OR Function .............................................................................................. 89
Figure 12.1: Application Circuit for Radio Characteristics Specification with 8 x 8mm VFBGA Package .............. 92
Figure 13.1: BlueCore4-External 96-Ball VFBGA Package Dimensions ............................................................... 94
Figure 13.2: BlueCore4-External 96-Ball VFBGA Package Dimensions ............................................................... 95
Figure 14.1: Typical Lead-Free Re-flow Solder Profile.......................................................................................... 96
Figure 16.1: Tape and Reel Orientation ................................................................................................................ 98
Figure 16.2: Tape Dimensions .............................................................................................................................. 99
Figure 16.3: Reel Dimensions ............................................................................................................................. 100
BC417143B-ds-001Pc
© Copyright Cambridge Silicon Radio Limited 2004
Pre-Production Information
Page 5 of 107

5 Page





BC417143B-ES-IRN arduino
8 x 8mm VFBGA Package Information
PIO Port
PIO[11]
Ball
G3
PIO[10]
F3
PIO[9]
www.DataSheet4U.cPoImO[8]
E3
D3
PIO[7]
F10
PIO[6]/
WLAN_Active/
Ch_Data
PIO[5]/BT_Active
F11
E9
PIO[4]/ BT_Priority/Ch_Clk E10
PIO[3]
J3
PIO[2]
H3
AIO[0]
AIO[1]
AIO[2]
K1
J2
K2
Pad Type
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional
Bi-directional
Bi-directional
Description
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line or
Optionally WLAN_Active/Ch_Data input
for co-existence signalling
Programmable input/output line or
Optionally BT_Active output for
co-existence signalling
Programmable input/output line or
Optionally BT_Priority/Ch_Clk output for
co-existence signalling
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Test and Debug
RESETB
SPI_CSB
SPI_CLK
SPI_MOSI
SPI_MISO
TEST_EN
Ball Pad Type
Description
B10 CMOS input with weak
internal pull-up
Reset if low. Input debounced so must be
low for >5ms to cause a reset
C11 CMOS input with weak
internal pull-up
Chip select for Synchronous Serial
Interface active low
C10 CMOS input with weak
internal pull-down
Serial Peripheral Interface clock
D10 CMOS input with weak
internal pull-down
Serial Peripheral Interface data input
C9 CMOS output, tri-state, with Serial Peripheral Interface data output
weak internal pull-down
C8 CMOS input with strong
internal pull-down
For test purposes only (leave
unconnected)
BC417143B-ds-001Pc
© Copyright Cambridge Silicon Radio Limited 2004
Pre-Production Information
Page 11 of 107

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