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PDF 7TDMI Data sheet ( Hoja de datos )
| Número de pieza | 7TDMI | |
| Descripción | general purpose 32-bit microprocessors | |
| Fabricantes | ETC | |
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ARM 7TDMI
Data Sheet
Document Number:ARM DDI 0029E
Issued: August 1995
Copyright Advanced RISC Machines Ltd (ARM) 1995
All rights reserved
Proprietary Notice
ARM, the ARM Powered logo, EmbeddedICE, BlackICE and ICEbreaker are trademarks of
Advanced RISC Machines Ltd.
Neither the whole nor any part of the information contained in, or the product described in, this
datasheet may be adapted or reproduced in any material form except with the prior written
permission of the copyright holder.
The product described in this datasheet is subject to continuous developments and
improvements. All particulars of the product and its use contained in this datasheet are given by
ARM in good faith. However, all warranties implied or expressed, including but not limited to
implied warranties or merchantability, or fitness for purpose, are excluded.
This datasheet is intended only to assist the reader in the use of the product. ARM Ltd shall not
be liable for any loss or damage arising from the use of any information in this datasheet, or any
error or omission in such information, or any incorrect use of the product.
Change Log
Issue
Date
By Change
A (Draft 0.1)
(Draft 0.2)
B
C
D draft1
D
E
Sept 1994
Oct 1994
Dec 1994
Dec 1994
Mar 1995
Mar 1995
Mar 1995
Aug 1995
EH/BJH
EH
EH/AW
AW
AW
AW
AW
AP
Created.
First pass review comments added.
First formal release
Further review comments
Reissued with open access status.
No change to the content.
Changes in line with the ARM7TDM
datasheet. Further technical changes.
Review comments added.
Signals added plus minor changes.
ARM
Advanced RISC Machines
1 page  
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5.18 Format 18: unconditional branch
5.19 Format 19: long branch with link
5.20 Instruction Set Examples
6 Memory Interface
6.1 Overview
6.2 Cycle Types
6.3 Address Timing
6.4 Data Transfer Size
6.5 Instruction Fetch
6.6 Memory Management
6.7 Locked Operations
6.8 Stretching Access Times
6.9 The ARM Data Bus
6.10 The External Data Bus
7 Coprocessor Interface
7.1 Overview
7.2 Interface Signals
7.3 Register Transfer Cycle
7.4 Privileged Instructions
7.5 Idempotency
7.6 Undefined Instructions
8 Debug Interface
8.1 Overview
8.2 Debug Systems
8.3 Debug Interface Signals
8.4 Scan Chains and JTAG Interface
8.5 Reset
8.6 Pullup Resistors
8.7 Instruction Register
8.8 Public Instructions
8.9 Test Data Registers
8.10 ARM7TDMI Core Clocks
8.11 Determining the Core and System State
8.12 The PC’s Behaviour During Debug
8.13 Priorities / Exceptions
8.14 Scan Interface Timing
8.15 Debug Timing
ARM7TDMI Data Sheet
ARM DDI 0029E
Contents
5-39
5-40
5-42
6-1
6-2
6-2
6-4
6-9
6-10
6-12
6-12
6-12
6-13
6-15
7-1
7-2
7-2
7-3
7-3
7-4
7-4
8-1
8-2
8-2
8-3
8-6
8-8
8-9
8-9
8-9
8-12
8-18
8-19
8-23
8-25
8-26
8-30
Contents-iii
5 Page 
Introduction
1.2.2 THUMB’s Advantages
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THUMB instructions operate with the standard ARM register configuration, allowing
excellent interoperability between ARM and THUMB states. Each 16-bit THUMB
instruction has a corresponding 32-bit ARM instruction with the same effect on the
processor model.
The major advantage of a 32-bit (ARM) architecture over a 16-bit architecture is its
ability to manipulate 32-bit integers with single instructions, and to address a large
address space efficiently. When processing 32-bit data, a 16-bit architecture will take
at least two instructions to perform the same task as a single ARM instruction.
However, not all the code in a program will process 32-bit data (for example, code that
performs character string handling), and some instructions, like Branches, do not
process any data at all.
If a 16-bit architecture only has 16-bit instructions, and a 32-bit architecture only has
32-bit instructions, then overall the 16-bit architecture will have better code density,
and better than one half the performance of the 32-bit architecture. Clearly 32-bit
performance comes at the cost of code density.
THUMB breaks this constraint by implementing a 16-bit instruction length on a 32-bit
architecture, making the processing of 32-bit data efficient with a compact instruction
coding. This provides far better performance than a 16-bit architecture, with better
code density than a 32-bit architecture.
THUMB also has a major advantage over other 32-bit architectures with 16-bit
instructions. This is the ability to switch back to full ARM code and execute at full
speed. Thus critical loops for applications such as
• fast interrupts
• DSP algorithms
can be coded using the full ARM instruction set, and linked with THUMB code. The
overhead of switching from THUMB code to ARM code is folded into sub-routine entry
time. Various portions of a system can be optimised for speed or for code density by
switching between THUMB and ARM execution as appropriate.
ARM7TDMI Data Sheet
ARM DDI 0029E
1-3
11 Page | ||
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| PDF Descargar | [ Datasheet 7TDMI.PDF ] | |
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