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Silicon Laboratories |
C8051F231
25 MIPS, 8 kB Flash, 32-Pin Mixed-Signal MCU
Analog Peripherals
Two comparators
- Programmable hysteresis
- Configurable to generate interrupts or reset
VDD Monitor and Brown-out Detector
On-Chip JTAG Debug
- On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
- Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
- Superior performance to emulation systems using ICE-chips, target
pods, and sockets
- Fully compliant with IEEE 1149.1 specification
Supply Voltage: 2.7 to 3.6 V
www.DataSheet4U- .cToympical operating current: 9 mA at 25 MHz
- Typical stop mode current: <0.1 µA
Temperature Range: –40 to +85 °C
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
- Up to 25 MIPS throughput with 25 MHz system clock
- Expanded interrupt handler; up to 21 interrupt sources
Memory
- 256 bytes data RAM
- 8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are
reserved)
Digital Peripherals
- 22 port I/O; all are 5 V tolerant
- Hardware SPI™ and UART serial ports available concurrently
- 3 general-purpose 16-bit counter/timers
- Dedicated watchdog timer; bidirectional reset
Clock Sources
- Internal programmable oscillator: 2–16 MHz
- External oscillator: Crystal, RC, C, or Clock
- Can switch between clock sources on-the-fly
Package
- 32-pin LQFP (standard lead and lead-free packages)
Part Ordering Numbers
- Lead-free package: C8051F231-GQ
- Standard package: C8051F231
VDD
GND
Analog/Digital
Power
TCK
TMS
TDI
TDO
RST
XTAL1
XTAL2
JTAG
Logic
VDD
Monitor
External
Oscillator
Circuit
Internal
Oscillator
Debug HW
8
0
5Reset
1
WDT
System Clock
C
o
r
e
8 kB FLASH
256 byte
RAM
SFR Bus
Port 0
Latch
UART
P
0
Timer 0
Timer 1
Timer 2
M
U
X
Port 1
Latch
CP0 CP0
CP1 CP1
CP0+
CP0-
CP1+
CP1-
P
1
M
U
X
SYSCLK
Port 2
Latch
SPI
P
2
M
U
X
Port 3
Latch
P
0
P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
D P0.4/T0
r
v
P0.5/T1
P0.6/T2
P0.7/T2EX
P
1
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
D P1.4/CP1-
r
v
P1.5/CP1
P1.6/SYSCLK
P1.7
P
2
P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
D P2.4
r P2.5
v
P
3
D
r
v
NC
General Purpose
Copyright © 2005 by Silicon Laboratories
5.5.2005
C8051F231
25 MIPS, 8 kB Flash, 32-Pin Mixed-Signal MCU
Selected Electrical Specifications
(TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified unless otherwise specified)
PARAMETER
CONDITIONS
GLOBAL CHARACTERISTICS
Supply Voltage
Supply Current (CPU
Clock = 25 MHz
active)
Clock = 1 MHz
Clock = 32 kHz; VDD Monitor Disabled
Supply Current
(shutdown)
Oscillator not running; VDD Monitor
Enabled
Oscillator not running; VDD Monitor
Disabled
www.DataSheet4U.coCmlock Frequency Range
COMPARATORS
Supply Current
(each comparator)
Response Time
(CP+) – (CP-) = 100 mV
MIN
2.7
DC
TYP
9
0.4
11
10
0.1
1.5
4.0
MAX
3.6
25
UNITS
V
mA
mA
µA
µA
µA
MHz
µA
µs
Package Information
D
D1
MIN NOM MAX
(mm) (mm) (mm)
A-
- 1.60
E1 E
A1 0.05 - 0.15
A2 1.35 1.40 1.45
b 0.30 0.37 0.45
32
PIN 1
IDENTIFIER
A2
1
b
A
A1
e
D - 9.00 -
D1 - 7.00 -
e - 0.80 -
E - 9.00 -
E1 - 7.00 -
C8051F226DK Development Kit
General Purpose
Copyright © 2005 by Silicon Laboratories
5.5.2005
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
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