PDF ZL10039 Data sheet ( Hoja de datos )

Número de pieza	ZL10039
Descripción	Digital Satellite Tuner
Fabricantes	Zarlink Semiconductor
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No Preview Available ! Features • Direct conversion tuner for quadrature down conversion from L-band to Zero IF • Symbol rate 1-45 MSps • Excellent sensitivity <-84.5 dBm at 27.5 MSps • Independent RF AGC and baseband gain control • Fifth order baseband filters with bandwidth www.DataSheet4Ua.cdojmustable from 6 to 43 MHz • Fully integrated alignment-free low phase noise local oscillator • Selectable RF Bypass • I2C compatible control • 3.3 Volt Supply • 28 pin 5x5 mm QFN Package Applications • DVB-S Free-to-Air Satellite receiver systems • 8PSK Satellite Receiver Systems ZL10039 Digital Satellite Tuner with RF Bypass Data Sheet July 2005 Ordering Information ZL10039LCG 28 Pin QFN Trays ZL10039LCF 28 Pin QFN Tape and Reel ZL10039LCG1 28 Pin QFN* Trays ZL10039LCF1 28 Pin QFN* Tape and Reel *Pb Free Matte Tin -10°C to +85°C Description The ZL10039 is a fully integrated direct conversion tuner for digital satellite receiver systems, targeted primarily at free-to-air DVB-S receivers where high sensitivity is a priority. The device also contains a RF Bypass for connecting to a second receiver module. The ZL10039 is simple to use, requiring no alignment or tuning algorithms and uses a minimum number of external components. The device is programmable via a I2C compatible bus. A complete reference design (ZLE10541) is available using ZL10313 demodulator. RF Input ZL10039 Bypass Output Quadrature VCO PLL RF AGC I Q I2C Control Loop Filter Crystal Figure 1 - Basic Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved. 1 page ZL10039 Data Sheet VccRF1 VccRF2 RFAGC www.DataSheet4U.com RFIN LNA AGC RFBYPASS VccLO LOTEST Vvar PAD/REF VccVCO VccDIG SDA SCL SLEEP XTAL XCAP (PADDLE) VCO BANK REF OSC BF BANDWIDTH ADJUST FILTER DC CORRECTION DC CORRECTION FILTER 90 deg 0 deg PHASE SPLITTER LOCK DETECT 15 BIT PROGRAMMABLE DIVIDER I2C BUS INTERFACE Fpd CHARGE PUMP Fcomp PORT INTERFACE VccBB QOUT QOUT IOUT IOUT VccCP PUMP P0 REFERENCE DIVIDER Figure 3 - Detailed Block Diagram 5 Zarlink Semiconductor Inc. 5 Page ZL10039 Data Sheet The R[3:0] bits select the Reference Divider divide ratio. The ratio selected is not a simple binary power-of-two value but through a lookup table, see Table 7- PLL Reference Divider Ratios. www.DataSheet4U.com R3 R2 R1 R0 Division Ratio 00002 00014 00108 0 0 1 1 16 0 1 0 0 32 0 1 0 1 64 0 1 1 0 128 0 1 1 1 256 10003 10015 1 0 1 0 10 1 0 1 1 20 1 1 0 0 40 1 1 0 1 80 1 1 1 0 160 1 1 1 1 320 Table 7 - PLL Reference Divider Ratios Bit Field Name Default Type Description 7:0 - 0X40 R/W Test Modes Table 8 - Register 3 This register controls test modes within the PLL. This should be programmed with the default settings. 2.2 RF Control Register A single register controls RF programmability. Bit Field 7 6:2 1 0 Name - - LEN - Default Type Description - R Test Modes 11011 R/W Test Modes 1 R/W Bypass Enable 0 R/W Not used Table 9 - Register 4 11 Zarlink Semiconductor Inc. 11 Page

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