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PDF ZL10036 Data sheet ( Hoja de datos )
| Número de pieza | ZL10036 | |
| Descripción | Digital Satellite Tuner | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ZL10036 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ZL10036
Digital Satellite Tuner with RF Bypass
Data Sheet
Features
• QPSK tuner for quadrature down conversion from
L-band to Zero IF
• Compatible with DSS and DVB formats (QPSK)
• Symbol rate range 1 to 45 MSps
• Power & forget, fully integrated, alignment free,
local oscillator
• Integrated baseband filters with bandwidth adjust
www.DataSheet4Uf.rcoomm 4 to 40 MHz
• Good immunity to strong adjacent undesired
channels
• Selectable RF bypass
• I²C bus interface with 3V3 compatible logic levels
• Integrated RF loop through for cascaded tuner
applications
• Power saving mode/hardware power down
• Optimized front end solution when partnered with
Zarlink ZL10312 demodulator
Applications
• Satellite receiver systems
July 2004
Ordering Information
ZL10036LDG 40-pin QFN
ZL10036LDF 40-pin QFN
ZL10036LDG1 40-pin QFN*
ZL10036LDF1 40-pin QFN*
(trays)
(tape and reel)
(trays)
(tape and reel)
*Pb free
-10°C to +85°C
Description
The ZL10036 is a single chip wideband direct
conversion tuner, with integral RF bypass, optimized
for application in digital satellite receiver systems.
The device offers a highly integrated solution to a
satellite tuner function, incorporating an I²C bus
interface controller, a low phase noise PLL frequency
synthesizer, a quadrature phase split tuner, a fully
integrated local oscillator which requires no production
set up, and adjustable baseband channel filters.
The I²C bus interface controls all of the tuner
functionality including the PLL frequency synthesizer,
the bypass disable and the baseband gain and
bandwidth adjust.
Figure 1 - Basic Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL10036
Data Sheet
List of Figures
Figure 1 - Basic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Typical Application Circuit ZLE10532 (SNIM-9r2) using ZL10312 Demodulator . . . . . . . . . . . . . . . . . . . 2
Figure 3 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4 - AGC Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5 - Typical First Stage RF AGC Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6 - Variation in IIP2 with AGC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7 - Variation in IIP3 with AGC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8 - Variation in NF with Input Amplitude (typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9 - RF input and Output (bypass) Return Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10 - Normalized Filter Transfer Characteristic (Setting 20 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
www.DataSheeFFt4iiggUuu.crroeem1112
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LO Phase Noise Performance . . . . . . .
Copper Dimensions for Optimum Heat
.......
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Figure 13 - Paste Mask for Reduced Paste Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 14 - Typical Oscillator Arrangement with Optional Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 15 - Typical Arrangement for External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5
Zarlink Semiconductor Inc.
5 Page 
Pin Symbol Direction
ZL10036
Function
35 PTEST
In
Connected to internal circuit for
monitoring die temperature
Data Sheet
Schematics
PTEST
36 VccLO
37 VccLO
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38 LOTEST
+5 V voltage supply for LO
+5 V voltage supply for LO
Bi-directional test port for accessing
IO internal LO
AC couple input.
VccLO
LOTEST
Bias
39 P1
Switching port P1
Out ‘0’ = disabled (high impedance)
‘1’ = enabled
40 CNT
Bonded to paddle. Production continuity
test for paddle soldering
Note: Exposed paddle on rear of package must be connected to GND
Same configuration as pin 24,
P0
1.0 Overview
1.1 Conventions in this Manual
Hexadecimal values are typically shown as 0xABCDEF. Binary values (usually of register bits) are shown as
011002. All other numbers should be considered to be decimal values unless specified otherwise.
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ZL10036.PDF ] | |
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