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AN111 반도체 회로 부품 판매점

Using the Xicor 16K to 64K Supervisory EEPROMs



Xicor 로고
Xicor
AN111 데이터시트, 핀배열, 회로
Application Note
AN111
Using the Xicor X5163/X5323/X5643 CPU Supervisors with the
68HC11 Microcontroller
by Applications Staff, September 1998
Description
The following code demonstrates how Xicor's CPU Super-
visors with EEPROM can be interfaced to the 68HC11
microcontroller when connected as shown in Figure 1.
The circuit uses the 68HC11’s built-in SPI port with the
PD4/SCK pin connected to the serial clock (SCK), the
PD3/MOSI pin connected to serial data in (SI), the PD2/
MISO pin connected to serial data out (SO), and the PD5/
www.DaPtCaSSh0e/eCt4SU.cpoinm connected to chip select (CS). The SPI
interface of the CPU Supervisors operate at 2MHz, so the
68HC11 can operate the SPI port at the maximum speed.
This code allows the 68HC11 to read and write data from
the EEPROM and select EEPROM Block Lock configura-
tions. It also allows the 68HC11 to change the watchdog
timer settings (if available) or turn off the watchdog timer.
More Information
Additional code can be found on the Xicor WWW site at
http://www.xicor.com.
RESET
U?
30 XT
29 EX
39 RESET
41
40
IRQ
XIRQ
8 PA0
7
6
PA1
PA2
17 PE0
18 PE1
19
20
PE2
PE3
22 VRH
21 VRL0
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
MODA
MODB
E
AS
R/W
5
4
3
2
1
16
15
14
13
12
11
10
9
31
32
33
34
35
36
37
38
42
43
44
45
46
47
25
24
27
26
28
U?
2
5
6
SO
SI
SCK
1 CS
7
RESET
3
WP
Vcc
R?
10K
RESET
X5163, X5168
X5323, X5328
X5643, X5648
Figure 1. Interfacing the Xicor CPU Supervisors to the 68HC11 Microcontroller using the SPI Port
AN111-1


AN111 데이터시트, 핀배열, 회로
Xicor Application Note
AN111
********************************************************************************
** DESCRIPTION:
** The purpose of this program is to show the use of the M68HC11
** assembly language to program the XICOR CPU Supervisor device. The "WIP"
** status polling (ACKPOL program) is a unique feature of the SPI memories.
** The processor interfaces the EEPROM through its Serial Peripheral
** Interface Port (SPI). The SCK pin is connected to the serial clock (SCK),
** MOSI to serial data in(SI), MISO to the serial data out (SO), and PCS0/CS
** to the CS input of the EEPROM. The main section of the code calls up other
** modules in order to demonstrate the procedure to be followed when
** reading/writing from/to the device. Routines are provided that write and
** read data to/from the status register, including BlockLock and Watchdog
** Timer bits.
**
** This code supports the following supervisory products:
**
** X5163, X5165, X5168, X5169*
** X5323, X5325, X5328, X5329*
** X5643, X5645, X5648, X5649*
www.Da*t*aSheet4U.com
** * These devices have no Watchdog Timer, so write ‘0’ to the Wdx bits.
*******************************************************************************
*******************************************************************************
* INTERNAL RAM LOCATIONS
ADDRL
EQU $FF
MEMORY ADDRESS LOW BYTE
ADDRH
EQU ADDRL-1
MEMORY ADDRESS HIGH BYTE
PATTERN
EQU ADDRH-1
PATTERN REGISTER
STACK
EQU PATTERN-1 STACK TOP
* CONSTANTS
WREN_CMD
EQU 006
WRITE ENABLE
WRITE_CMD EQU 002
WRITE DATA TO EEPROM
READ_CMD
EQU 003
READ EEPROM DATA
WRDI_CMD
EQU 006
WRITE DISABLE
RDSR_CMD
EQU 005
READ STATUS REGISTER COMMAND
WRSR_CMD
EQU 001
WRITE STATUS REGISTER COMMAND
DUMMY
EQU $FF
DUMMY STATUS OF MOSI PIN DURING BYTE READ
SPE_BIT
EQU $40
SPIF_BIT
EQU $80
BIT POSITION OF THE SPIF
CE_BIT
EQU $20
BIT POSITION FOR PCS0/CS
* EQUATES FOR USE WITH INDEX OFFSET = $1000
PORTD
EQU $08
DDRD
EQU $09
SPCR
EQU $28
SPDR
EQU $2A
SPSR
EQU $29
BAUD
EQU $2B
SCDAT
EQU $2F
SCSR
EQU $2E
SCCR2
EQU $2D
STAT_BYTE EQU $00
Turn off BlockLock, Set WDT=1.4s
* ASSEMBLER REQUIREMENT- CPU TYPE
P68H11
PAGE
* START OF USER CODE
ORG $E000
TEST:
lds #STACK
* LOAD STACK POINTER
ldx #$1000
* SET REGISTER BASE
* INITIALIZE THE SPI
ldaa #$3F
staa DDRD,X
* PORT-D PINS ALL SET AS OUTPUTS
ldaa #$50
staa SPCR,X
* MODE = 0, CLK = 1MHZ
ldaa #$00
staa PATTERN
* DATA PATTERN TO WRITE
AN111-2




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