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PDF ML145159 Data sheet ( Hoja de datos )
| Número de pieza | ML145159 | |
| Descripción | Serial-Input PLL Frequency Synthesizer | |
| Fabricantes | LANSDALE Semiconductor | |
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ML145159
Serial-Input PLL Frequency
Synthesizer with Analog Phase
Detector
INTERFACES WITH DUAL–MODULUS PRESCALERS
Legacy Device: Motorola MC145159-1
The ML145159 has a programmable 14–bit reference
counter, as well as fully programmable
divide–by–N/divide–by–A counters. The counters are pro-
grammed serially through a common data input and
latched into the appropriate counter latch, according to the
last data bit (control bit) entered.
When combined with a loop filter and VCO, this device can
provide all the remaining functions for a PLL frequency syn-
thesizer operating up to the device's frequency limit. For high-
er VCO frequency operations, a down mixer or a dual–modu-
lus prescaler can be used between the VCO and the PLL.
• Operating Temperature Range: TA – 40° to 85°C
• Low Power Consumption Through Use of CMOS
Technology
• 3.0 to 9.0 V Supply Range
• On– or Off–Chip Reference Oscillator Operation
• Compatible with the Serial Peripheral Interface (SPI)
on CMOS MCUs
• ÷ R Range = 3 to 16383
• ÷ N Range = 16 to 1023, P A Range = 0 to 127
• High–Gain Analog Phase Detector
• See Application Note AN969
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
Page 1 of 10
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Issue A
1 page  
ML145159
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PIN DESCRIPTIONS
INPUT PINS
OSCin, OSCout
Oscillator Input and Oscillator Output (PDIP, SOG –
Pins 2, 3; SSOP – Pins 7, 8)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel–resonant crystal.
Frequency–setting capacitors of appropriate value must be con-
nected from OSCin to VSS and OSCout toVSS. OSCin may
also serve as input for an externally–generated reference sig-
nal. This signal will typically be AC coupled to OSCin, but for
larger amplitude signals (standard CMOS logic levels), DC
coupling may also be used. In the external reference mode, no
connection is required to OSCout.
fin
Frequency Input (PDIP, SOG – Pin 10, SSOP – Pin 15)
Input to the positive edge triggered divide–by–N and di-
vide–by–A counters. fin is typically derived from a dual–mod-
ulus prescaler and is AC coupled. This input has an inverter
biased in the linear region to allow use with AC coupled sig-
nals as low as 500 mV peak–to–peak or direct coupled signals
swinging from VDD to VSS.
DATA
Serial Data Input (PDIP, SOG – Pin 12, SSOP – Pin 17)
Counter and control information is shifted into this input.
The last data bit entered goes into the one–bit control shift reg-
ister. A logic 1 allows the reference counter information to be
loaded into its 14–bit latch when ENB goes high. A logic 0
entered as the control bit disables the reference counter latch.
The divide–by–A/divide–by–N counter latch is loaded, regard-
less of the contents of the control register, when ENB goes
high. The data entry format is shown in Figure 1.
ENB
Transparent Latch Enable (PDIP, SOG – Pin 13,
SSOP – Pin 18)
A logic high on this input allows data to be entered into the
divide–by–A/divide–by–N latch and, if the control bit is high,
into the reference counter latch. Counter programming is unaf-
fected when ENB is low. ENB should be kept normally low
and pulsed high to transfer data to the latches.
CLK
Shift Register Clock (PDIP, SOG – Pin 11, SSOP – Pin 16)
A low–to–high transition on this input shifts data from the
serial data input into the shift registers.
LANSDALE Semiconductor, Inc.
COMPONENT PINS
CR
Ramp Capacitor (PDIP, SOG – Pin 15, SSOP – Pin 20)
The capacitor connected from this pin to VSS’ is charged lin-
early, at a rate determined by RR. The voltage on this capacitor
is proportional to the phase difference of the frequencies pres-
ent at the internal phase detector inputs. A polystyrene or
mylar capacitor is recommended.
RR
Ramp Current Bias Resistor (PDIP, SOG – Pin 20,
SSOP – Pin 5)
A resistor connected from this pin to VSS’ determines the
rate at which the ramp capacitor is charged, thereby affecting
the phase detector gain (see Figure 2).
CH
Hold Capacitor (PDIP, SOG – Pin 18, SSOP – Pin 3)
The charge stored on the ramp capacitor is transferred to the
capacitor connected from this pin to either VDD’ or VSS’. The
ratio of CR to CH should be large enough to have no effect on
the phase detector gain (CR > 10 CH). A low–leakage capaci-
tor should be used.
RO
Output Bias Current Resistor (PDIP, SOG – Pin 1,
SSOP – Pin 6)
A resistor connected from this pin to VSS’ biases the output
N–Channel transistor, thereby setting a current sink on the ana-
log phase detector output. This resistor adjusts the APDout bias
current (see Figure 3).
OUTPUT PINS
APDout
Analog Phase Detector Output (PDIP, SOG – Pin 17,
SSOP – Pin 2)
This output produces a voltage that controls an external
VCO. The voltage range of this output (VDD = + 9 V) is from
below + 0.5 V to + 8 V or more. The source impedance of this
output is the equivalent of a source follower with an externally
variable source resistor. The source resistor depends upon the
output bias current controlled by the output bias current resis-
tor, RO. The bias current is adjustable from 0.01 mA to 0.5
mA. The output voltage is not more than 1.05 V below the
sampled point on the ramp. With a constant sample of the
ramp voltage at 9 V and the hold capacitor of 50 pF, the instan-
taneous output ripple is about 5 mV peak–to–peak.
Page 5 of 10
Figure 1. Data Entry Format
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Issue A
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet ML145159.PDF ] | |
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