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PDF 39SF512 Data sheet ( Hoja de datos )

Número de pieza 39SF512
Descripción SST39SF512
Fabricantes SST 
Logotipo SST Logotipo



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No Preview Available ! 39SF512 Hoja de datos, Descripción, Manual

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512 Kbit (x8) Multi-Purpose Flash
SST39SF512
FEATURES:
SST39SF5125.0V 512Kb (x8) MPF memory
Data Sheet
• Organized as 64K x8
• Single 4.5-5.5V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
(typical values at 14 MHz)
– Active Current: 10 mA (typical)
– Standby Current: 10 µA (typical)
• Sector-Erase Capability
– Uniform 4 KByte sectors
• Fast Read Access Time:
– 70 ns
• Latched Address and Data
• Fast Erase and Byte-Program
– Sector-Erase Time: 7 ms (typical)
– Chip-Erase Time: 15 ms (typical)
– Byte-Program Time: 20 µs (typical)
– Chip Rewrite Time: 2 seconds (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 32-pin PDIP
PRODUCT DESCRIPTION
The SST39SF512 are CMOS Multi-Purpose Flash (MPF)
manufactured with SST’s proprietary, high performance
CMOS SuperFlash technology. The split-gate cell design
and thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST39SF512 devices write (Program or Erase) with a
4.5-5.5V power supply. The SST39SF512 device conforms
to JEDEC standard pinouts for x8 memories.
Featuring high performance Byte-Program, the
SST39SF512 devices provide a maximum Byte-Program
time of 30 µsec. These devices use Toggle Bit or Data#
Polling to indicate the completion of Program operation. To
protect against inadvertent write, they have on-chip hard-
ware and Software Data Protection schemes. Designed,
manufactured, and tested for a wide spectrum of applica-
tions, these devices are offered with a guaranteed typical
endurance of 100,000 cycles. Data retention is rated at
greater than 100 years.
The SST39SF512 devices are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
they significantly improve performance and reliability, while
lowering power consumption. They inherently use less
energy during erase and program than alternative flash
technologies. The total energy consumed is a function of
©2003 Silicon Storage Technology, Inc.
S71149-05-000
11/03
1
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST39SF512 are offered in 32-lead PLCC, 32-lead TSOP,
and a 600 mil, 32-pin PDIP packages. See Figures 1, 2,
and 3 for pin assignments.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.

1 page




39SF512 pdf
www.DataSheet4U.com
512 Kbit Multi-Purpose Flash
SST39SF512
Data Sheet
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die Up
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)
32 OE#
31 A10
30 CE#
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 VSS
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
1149 F01.3
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6 32-pin
7 PDIP
8 Top View
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
1149 F02a.4
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP
©2003 Silicon Storage Technology, Inc.
5
S71149-05-000
11/03

5 Page





39SF512 arduino
www.DataSheet4U.com
512 Kbit Multi-Purpose Flash
SST39SF512
Data Sheet
ADDRESS AMS-0
CE#
TAS
OE#
5555
TAH
TCP
2AAA
TCPH
5555
ADDR
INTERNAL PROGRAM OPERATION STARTS
TBP
TDH
TDS
WE#
TCH
DQ7-0
TCS
AA 55
A0 DATA
SW0
SW1 SW2
Note: AMS = Most significant address
AMS = A15 for SST39SF512
BYTE
(ADDR/DATA)
1149 F05.2
FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0
CE#
OE#
WE#
TOEH
TCE
TOE
DQ7
D D#
Note: AMS = Most significant address
AMS = A15 for SST39SF512
FIGURE 7: DATA# POLLING TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
11
D#
TOES
D
1149 F06.2
S71149-05-000
11/03

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