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PDF RK80546HE0721M Data sheet ( Hoja de datos )
| Número de pieza | RK80546HE0721M | |
| Descripción | Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology | |
| Fabricantes | Intel | |
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Mobile Intel® Pentium® 4
Processor Supporting
Hyper-Threading Technology on
90-nm Process Technology
Datasheet
January 2005
Document Number: 302424-003
1 page  
www.DataSheet4U.com
Figures
2-1
2-2
2-3
3-1
3-2
3-3
3-4
3-5
4-1
4-2
5-1
5-2
6-1
Phase Lock Loop (PLL) Filter Requirements ...................................................... 14
Vcc Static and Transient Tolerance1, 2, 3 .......................................................... 22
VCC Overshoot Example Waveform................................................................... 26
Processor Package Assembly Sketch.................................................................27
Processor Package Drawing Sheet 1 of 2........................................................... 29
Processor Package Drawing Sheet 2 of 2........................................................... 30
Processor Top-Side Markings ............................................................................. 32
Processor Pin-Out Coordinates, Top View.......................................................... 33
Pinout Diagram (Top View—Left Side) ............................................................... 48
Pinout Diagram (Top View—Right Side) ............................................................. 49
Case Temperature (TC) Measurement Location................................................. 60
Intel Thermal Monitor 2 Frequency and Voltage Ordering .................................. 62
Stop Clock State Machine ................................................................................... 68
Tables
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
3-1
3-2
3-3
4-1
4-2
4-3
5-1
5-2
5-3
6-1
References ............................................................................................................ 9
Core Frequency to Front Side Bus Multiplier Configuration ................................ 12
Voltage Identification Definition ........................................................................... 13
Front Side Bus Pin Groups.................................................................................. 16
Signal Description Table ..................................................................................... 17
Signal Reference Voltages.................................................................................. 17
BSEL[1:0] Frequency Table for BCLK[1:0].......................................................... 18
Absolute Maximum and Minimum Ratings .......................................................... 19
Voltage and Current Specifications ..................................................................... 20
VCC Core Deep Sleep State Voltage Regulator Static and Transient Tolerance
(Deep Sleep VID Offset = 1.7%) ......................................................................... 22
GTL+ Signal Group DC Specifications ................................................................ 23
Asynchronous GTL+ Signal Group DC Specifications ........................................ 23
PWRGOOD and TAP Signal Group DC Specifications....................................... 24
VCCVID DC Specifications ................................................................................. 24
VIDPWRGD DC Specifications ........................................................................... 24
BSEL [1:0] and VID[5:0] DC Specifications......................................................... 25
BOOTSELECT DC Specifications....................................................................... 25
VCC Overshoot Specifications ............................................................................ 25
Processor Loading Specifications ....................................................................... 31
Package Handling Guidelines ............................................................................. 31
Processor Materials............................................................................................. 32
Alphabetical Pin Assignments ............................................................................. 35
Numerical Pin Assignment .................................................................................. 42
Signal Description ............................................................................................... 50
Processor Thermal Specifications....................................................................... 60
Thermal Diode Parameters ................................................................................. 64
Thermal Diode Interface...................................................................................... 65
Power-On Configuration Option Pins .................................................................. 67
Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Datasheet
5
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Electrical Specifications
2 Electrical Specifications
2.1
2.2
2.2.1
2.2.2
2.2.3
Power and Ground Pins
For clean on-chip power distribution, the processor has 85 VCC (power) and 179 VSS (ground) pins.
All power pins must be connected to VCC, while all VSS pins must be connected to a system ground
plane.The processor VCC pins must be supplied the voltage determined by the VID (Voltage
identification) pins.
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of
generating large current swings between low and full power states. This may cause voltages on
power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be
taken in the board design to ensure that the voltage provided to the processor remains within the
specifications listed in Table 2-8. Failure to do so can result in timing violations or reduced lifetime
of the component. For further information and design guidelines, refer to the Intel® 852GME and
Intel® 852PM Chipset Platforms Design Guide.
Vcc Decoupling
Regulator solutions need to provide bulk capacitance with a low effective series resistance (ESR)
and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the
large current swings when the part is powering on, or entering/exiting low power states, must be
provided by the voltage regulator solution (VR). For more details on this topic, refer to the Intel®
852GME and Intel® 852PM Chipset Platforms Design Guide.
Front Side Bus GTL+ Decoupling
The processor integrates signal termination on the die as well as incorporating high frequency
decoupling capacitance on the processor package. Decoupling must also be provided by the system
baseboard for proper GTL+ bus operation. For more information, refer to the Intel® 852GME and
Intel® 852PM Chipset Platforms Design Guide.
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor core frequency is a multiple of the
BCLK[1:0] frequency. No user intervention is necessary, and the processor will automatically run
at the speed indicated on the package. The processor uses a differential clocking implementation.
Mobile Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Datasheet
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