|
Samsung Electronics |
www.DataSheet4U.com
K8F56(57)15ET(B)M
NOR FLASH MEMORY
256Mb M-die MLC NOR Specification
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1 Revision 1.2
September, 2006
www.DataSheet4U.com
K8F56(57)15ET(B)M
NOR FLASH MEMORY
Document Title
256M Bit (16M x16) Muxed Burst , Multi Bank MLC NOR Flash Memory
Revision History
Revision No. History
0.0 Initial
0.1 Revision
tCEZ is changed.
20ns==>15ns
44FBGA PKG diagram is added
0.2 Package diagram is added (New format)
0.3 DPD pin assignment is changed
D6 ==> C7
AC parameters are changed
tBA : 8ns ==> 9ns (@83MHz)
tBDH : 1.5ns
==> 3ns (@66Mhz, 83MHz), 2ns (@133Mhz)
tOE : 20ns ==> 15ns
tRDYA : 8ns ==> 9ns (@83MHz)
tRDYS : 4ns (@66Mhz, 83MHz), 1.5ns (@133Mhz)
==> 3ns (@66Mhz, 83MHz), 2ns (@133Mhz)
tOER : 20ns
==> 11ns (@66Mhz), 9ns (@83MHz), 6ns (@133Mhz)
Active write current
15mA (Typ.), 30mA (Max.)
==> 25mA (Typ.), 40mA (Max.)
0.4 Correct typo
Add Speed characteristic for 108Mhz Sync Burst Read
Add Ordering Information for Density
==> 56 : 256Mb for 66/83MHz
==> 57 : 267Mb for 108/133Mhz
Add Product Classification Table (Table 1-1)
Change tAVDH(AVD Hold Time from CLK)
6ns(@66MHz) ==> 2ns(@66MHz)
5ns(@83MHz) ==> 2ns(@83MHz)
Change tAAVDH(Address Hold Time from Rising Edge of AVD)
7ns(@66MHz) ==> 2ns(@66MHz)
5ns(@83MHz) ==> 2ns(@83MHz)
Change tCES(CE Setup Time to CLK)
4.5ns(@83/133MHz) ==> 6ns(@83/133MHz)
Change tOEZ(Output Disable to High Z
10ns(@66/83MHz) ==> 15ns(@66/83MHz)
Add Description and Figure of DPD
0.5 Correct typo
Move address tables to the end of specification
Correct note number on Command Sequence table
Change tGHWL(Read Recovery Time Before Write)
0ns(typ.) ==> 0ns(min.)
Change tWP(WE Pulse Width)
60ns(typ.) ==> 60ns(min.)
Change tWPH(WE Pulse Width High)
40ns(typ.) ==> 40ns(min.)
Draft Date
October 17, 2005
Remark
Preliminary
October 19, 2005 Preliminary
October 26,2005 Preliminary
November 10,2005 Preliminary
December 20,2005 Preliminary
January 05,2006 Preliminary
2 Revision 1.2
September, 2006
|