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Número de pieza | 74LS109A | |
Descripción | LOW POWER SCHOTTKY | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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SN74LS109A
Dual JK Positive
Edge-Triggered Flip-Flop
The SN74LS109A consists of two high speed completely
independent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform. The JK
design allows operation as a D flip-flop by simply connecting the J and
K pins together.
MODE SELECT – TRUTH TABLE
OPERATING MODE
INPUTS
SD CD
J
OUTPUTS
KQQ
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Hold
Toggle
Load “0” (Reset)
LHXXHL
HLXXLH
L L XXHH
HHh hHL
HH l h q q
HHh l q q
HH
l
l
LH
* Both outputs will be HIGH while both SD and CD are LOW, but the output
states are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input
i, h (q) = (or output) one set-up time prior to the LOW to HIGH clock transition.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
TA Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current – High
IOL Output Current – Low
– 0.4
8.0
mA
mA
http://onsemi.com
LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
Package
Shipping
SN74LS109AN 16 Pin DIP 2000 Units/Box
SN74LS109AD
16 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1
Publication Order Number:
SN74LS109A/D
1 page |
Páginas | Total 4 Páginas | |
PDF Descargar | [ Datasheet 74LS109A.PDF ] |
Número de pieza | Descripción | Fabricantes |
74LS109 | Dual J-K Flip-Flop | Agere Systems |
74LS109A | LOW POWER SCHOTTKY | ON Semiconductor |
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