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RD151TS501US 반도체 회로 부품 판매점

PLL clock generator series



Renesas Technology 로고
Renesas Technology
RD151TS501US 데이터시트, 핀배열, 회로
www.DataSheet4U.com
RD151TS501US
PLL clock generator series
REJ03D0897-0102
Rev.1.02
Apr 25, 2007
Description
RD151TS501US is phase-locked loop clock generator with high-performance. And RD151TS501US is low-jitters and
will enable high density mounting by shrink small-size package (SSOP-8).
Features
Input frequency:
Output frequency:
27.0 to 36.0 MHz
54.0 to 72.0 MHz (1 : 2), 67.5 to 72.0 MHz (1 : 2.5)
27.0 to 36.0 MHz (1 : 1), 33.75 to 36.0 MHz (1 : 1.25) (Selectable)
Key Specifications
Supply voltages: VDD = 2.7 to 3.6 V
Operating temperature = -10 to 75 °C
Cycle to cycle jitter = ±75 ps typ.
Clock output duty cycle = 50±5%
Stabilization time: 2ms max
Power-down mode is supported
Ordering Information
Part Name
Package Type
RD151TS501USE
SSOP-8 pin
Package Code
(Previous Package Code)
PVSP0008KA–A
(TTP-8DBV)
Package
Abbreviation
US
Taping
Abbreviation (Quantity)
E (3,000 pcs / Reel)
Pin Arrangement
VDD 1
8 DIV2
VDD 2
7 IN
VSS 3
6 SEL
OUT 4
(Top view)
5 PDWN
REJ03D0897-0102 Rev.1.02 Apr 25, 2007
Page 1 of 6


RD151TS501US 데이터시트, 핀배열, 회로
RD151TS501US
Block Diagram
VDD
IN 1/M
Rpd = 100 k
Synthesizer
VSS
DIV
PDWN
SEL
DIV2
1/N
Rpd = 100 k
Rpd = 100 k
Rpd = 100 k
OUT
Pin Descriptions
Pin name
No.
Type
Description
VDD
1,2
Power
Power supply
VSS
3
Ground
GND
OUT
PDWN
SEL
IN
DIV2
4
5
6
7
8
Output
Input
Input
Input
Input
Clock signal output
Power-down control *1
Frequency select *1
Clock signal input *1
Frequency select *1
Note: 1. LVCMOS level input. Pull-down by internal resistor (100 k).
Power-down Function Table
Note:
PDWN
IC Operating
L Power-down
H Active
1. All Circuits are set stand-by condition.
OUTPUT
Low level
Clock signal output
Remark
Default *1
Clock Frequency Table
Note:
Output Frequency
SEL DIV2
(IN:OUT Ratio)
L L 54.0 to 72.0 MHz (1:2)
H L 67.5 to 72.0 MHz (1:2.5)
L H 27.0 to 36.0 MHz (1:1)
H H 33.75 to 36.0 MHz(1:1.25)
1. In case of selection of “SEL = H”, input frequency is limited 27 to 28.8 MHz.
Remark
Default
*1
*1
REJ03D0897-0102 Rev.1.02 Apr 25, 2007
Page 2 of 6




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PLL clock generator series - Renesas Technology