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AD5064 반도체 회로 부품 판매점

(AD50x4) DAC SPI Interface



Analog Devices 로고
Analog Devices
AD5064 데이터시트, 핀배열, 회로
Data Sheet
Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad,
SPI Interface, 4.5 V to 5.5 V in TSSOP
AD5024/AD5044/AD5064
FEATURES
Low power quad 12-/14-/16-bit DAC, ±1 LSB INL
Pin compatible and performance upgrade to AD5666
Individual and common voltage reference pin options
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero scale or midscale
3 power-down functions and per-channel power-down
Hardware LDAC with software LDAC override function
CLR function to programmable code
SDO daisy-chaining option
14-/16-lead TSSOP
Internal reference buffer and internal output amplifier
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAMS
VDD
VREFIN
AD5064-1
SCLK
SYNC
DIN
SDO
LDAC
INTERFACE
LOGIC AND
SHIFT
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
POWER-ON
RESET
DAC
REGISTER
DAC A
DAC B
DAC C
DAC D
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
VOUTD
POWER-DOWN
LOGIC
LDAC CLR
POR
GND
Figure 1. AD5064-1 Functional Equivalent and Pin Compatible with AD5666
AD5024/
AD5044/
AD5064 LDAC
SCLK
SYNC
DIN
INTERFACE
LOGIC AND
SHIFT
REGISTER
VDD
VREFA VREFB
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
POWER-ON
RESET
DAC
REGISTER
DAC A
DAC B
DAC C
DAC D
BUFFER
BUFFER
BUFFER
BUFFER
POWER-DOWN
LOGIC
VOUTA
VOUTB
VOUTC
VOUTD
LDAC CLR
POR
VREFC VREFD
GND
Figure 2. AD5024/AD5044/AD5064 with Individual Reference Pins
GENERAL DESCRIPTION
The AD5024/AD5044/AD5064/AD5064-1 are low power, quad
12-/14-/16-bit buffered voltage output nanoDAC® converters
that offer relative accuracy specifications of 1 LSB INL and 1 LSB
DNL with the AD5024/AD5044/AD5064 individual reference
pin and the AD5064-1 common reference pin options. The
AD5024/AD5044/AD5064/AD5064-1 can operate from a single
4.5 V to 5.5 V supply. The AD5024/AD5044/AD5064/AD5064-1
also offer a differential accuracy specification of ±1 LSB. The
parts use a versatile 3-wire, low power Schmitt trigger serial
interface that operates at clock rates up to 50 MHz and is compati-
ble with standard SPI, QSPI™, MICROWIRE™, and DSP interface
standards. Integrated reference buffers and output amplifiers are
also provided on-chip. The AD5024/AD5044/AD5064/AD5064-1
incorporate a power-on reset circuit that ensures the DAC
output powers up to zero scale or midscale and remains there
until a valid write takes place to the device. The AD5024/AD5044/
AD5064/AD5064-1 contain a power-down feature that reduces
the current consumption of the device to typically 400 nA at 5 V
and provides software selectable output loads while in power-
down mode. Total unadjusted error for the parts is <2 mV.
PRODUCT HIGHLIGHTS
1. Quad channel available in 14-/16-lead TSSOP packages.
2. 16-bit accurate, 1 LSB INL.
3. High speed serial interface with clock speeds up to 50 MHz.
4. Reset to known output voltage (zero scale or midscale).
Table 1. Related Devices
Part No.
AD5666
AD5025/AD5045/AD5065
AD5062, AD5063
AD5061
AD5040/AD5060
Description
Quad,16-bit buffered DAC,
16 LSB INL, TSSOP
Dual, 16-bit buffered DACs,
1 LSB INL, TSSOP
16-bit nanoDAC, 1 LSB INL, SOT-23,
MSOP
16-bit nanoDAC, 4 LSB INL, SOT-23
14-/16-bit nanoDAC, 1 LSB INL,
SOT-23
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


AD5064 데이터시트, 핀배열, 회로
AD5024/AD5044/AD5064
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 19
Digital-to-Analog Converter .................................................... 19
DAC Architecture....................................................................... 19
Reference Buffer ......................................................................... 19
Data Sheet
Output Amplifier........................................................................ 19
Serial Interface ............................................................................ 19
Shift Register ............................................................................... 19
Modes of Operation ................................................................... 21
Power-On Reset.......................................................................... 22
Power-Down Modes .................................................................. 22
Clear Code Register ................................................................... 23
LDAC Function .......................................................................... 23
Power Supply Bypassing and Grounding................................ 24
Microprocessor Interfacing....................................................... 25
Applications Information .............................................................. 26
Using a Reference as a Power Supply....................................... 26
Bipolar Operation....................................................................... 26
Using the AD5024/AD5044/AD5064/AD5064-1 with a
Galvanically Isolated Interface ................................................. 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 28
REVISION HISTORY
6/13—Rev. E to Rev. F
Change to Standalone Mode Section ........................................... 21
5/11—Rev. D to Rev. E
Changes to Table 4............................................................................ 5
Changes to Figure 4 and Figure 5................................................... 6
8/10—Rev. C to Rev. D
Change to Minimum SYNC High Time (Single Channel
Update) Parameter, Table 4 ............................................................. 5
5/10—Rev. B to Rev. C
Changes to Power-On Reset Section............................................ 22
6/09—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
3/09—Rev. 0 to Rev. A
Added 14-Lead TSSOP ......................................................Universal
Added Figure 1; Renumbered Sequentially .................................. 1
Changes to Features Section, General Description Section,
Product Highlights Section, Figure 2, and Table 1....................... 1
Changes to Table 2............................................................................ 3
Changes to Timing Characteristics Section and Table 4............. 5
Added Circuit and Timing Diagrams Section and Figure 3 ....... 5
Added Figure 5...................................................................................6
Changes to Figure 4...........................................................................6
Added Figure 6...................................................................................8
Added Table 6; Renumbered Sequentially .....................................8
Changed Input Shift Register to Shift Register Throughout .......8
Changes to Table 7.............................................................................9
Changes to Typical Performance Characteristics Section ........ 10
Changes to Terminology Section ................................................. 17
Changes to Digital-to-Analog Converter Section, Reference
Buffer Section, Output Amplifier Section, Serial Interface
Section, Shift Register Section, and Table 8................................ 19
Changes to Figure 47, Figure 48, and Figure 49 Captions ........ 20
Added Modes of Operation Section, Daisy-Chaining Section,
Table 10, and Table 11.................................................................... 21
Changes to Table 13 and Power-Down Mode Section .............. 22
Changes to Table 16 ....................................................................... 24
Changes to Figure 52 to Figure 55................................................ 25
Changes to Bipolar Operation Section and Figure 56 to
Figure 58 .......................................................................................... 26
Added Figure 59 ............................................................................. 27
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide .......................................................... 28
8/08—Revision 0: Initial Version
Rev. F | Page 2 of 28




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