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PDF 3D7324 Data sheet ( Hoja de datos )
| Número de pieza | 3D7324 | |
| Descripción | MONOLITHIC QUADRUPLE FIXED DELAY LINE | |
| Fabricantes | Data Delay Devices | |
| Logotipo |  |
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MONOLITHIC QUADRUPLE
FIXED DELAY LINE
(SERIES 3D7324)
3D7324
FEATURES
• All-silicon, low-power CMOS technology
• TTL/CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Leading- and trailing-edge accuracy
• Delay range: 6 through 6000ns
• Delay tolerance: 2% or 1.0ns
• Temperature stability: ±3% typ (-40C to 85C)
• Vdd stability: ±1% typical (4.75V to 5.25V)
• Minimum input pulse width: 20% of total delay
• 14-pin Gull-Wing available as drop-in
replacement for hybrid delay lines
PACKAGES
I1 1 14 VDD
N/C 2 13 N/C
I2 3 12 O1
I3 4 11 N/C
I4 5 10 O2
N/C 6 9 O3
GND 7 8 O4
3D7324-xx DIP
3D7324G-xx Gull-Wing
I1
N/C
I2
I3
I4
N/C
GND
1 14
2 13
3 12
4 11
5 10
69
78
VDD
N/C
O1
N/C
O2
O3
O4
3D7324D-xx
SOIC
(150 Mil)
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
The 3D7324 Quadruple Delay Line product family consists of fixed-
delay CMOS integrated circuits. Each package contains four matched,
independent delay lines. Delay values can range from 6ns through
6000ns. The input is reproduced at the output without inversion,
shifted in time as per the user-specified dash number. The 3D7324 is
TTL- and CMOS-compatible, capable of driving ten 74LS-type loads,
and features both rising- and falling-edge accuracy.
The all-CMOS 3D7324 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is
offered in a standard 14-pin auto-insertable DIP and a space saving
surface mount 14-pin SOIC.
PIN DESCRIPTIONS
I1
I2
I3
I4
O1
O2
O3
O4
VDD
GND
N/C
Delay Line 1 Input
Delay Line 2 Input
Delay Line 3 Input
Delay Line 4 Input
Delay Line 1 Output
Delay Line 2 Output
Delay Line 3 Output
Delay Line 4 Output
+5 Volts
Ground
No Connection
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
DIP-14 DIP-14 SOIC-14
3D7324 3D7324G 3D7324D
-6 -6
-6
-8 -8
-8
-10 -10
-10
-15 -15
-15
-20 -20
-20
-25 -25
-25
-30 -30
-30
-40 -40
-40
-50 -50
-50
-100
-100
-100
-200
-200
-200
-500
-500
-500
-1000
-1000
-1000
-6000
-6000
-6000
DELAY
PER LINE
(ns)
6 ± 1.0
8 ± 1.0
10 ± 1.0
15 ± 1.0
20 ± 1.0
25 ± 1.0
30 ± 1.0
40 ± 1.0
50 ± 1.0
100 ± 2.0
200 ± 4.0
-500
-1000
-6000
Max Operating
Frequency
55.5 MHz
41.6 MHz
33.3 MHz
22.2 MHz
16.7 MHz
13.3 MHz
11.1 MHz
8.33 MHz
6.67 MHz
3.33 MHz
1.67 MHz
500 ± 10.0
1000 ± 20
6000 ±120
INPUT RESTRICTIONS
Absolute Max Min Operating
Oper. Freq.
Pulse Width
125.0 MHz
9.0 ns
111.0 MHz
12.0 ns
100.0 MHz
15.0 ns
100.0 MHz
22.5 ns
100.0 MHz
30.0 ns
83.3 MHz
37.5 ns
71.4 MHz
45.0 ns
62.5 MHz
60.0 ns
50.0 MHz
75.0 ns
25.0 MHz
150.0 ns
12.5 MHz
300.0 ns
0.67 MHz
5.00 MHz
0.33 MHz
2.50 MHz
0.05 MHz
0.42 MHz
Absolute Min
Oper. P.W.
4.0 ns
4.5 ns
5.0 ns
5.0 ns
5.0 ns
6.0 ns
7.0 ns
8.0 ns
10.0 ns
20.0 ns
40.0 ns
750.0 ns
1500.0 ns
9000.0 ns
NOTES: Any delay between 10 and 6000 ns not shown is also available.
2006 Data Delay Devices
Doc #06016
5/10/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet 3D7324.PDF ] | |
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