3D3521 반도체 회로 부품 판매점
MONOLITHIC MANCHESTER ENCODER
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 Data Delay Devices |
www.DataSheet4U.com
MONOLITHIC MANCHESTER
ENCODER
(SERIES 3D3521)
3D3521
ddaeltaay 3
devices, inc.
FEATURES
• All-silicon, low-power CMOS
technology
• 3.3V operation
• CMOS compatible inputs and
outputs
• Vapor phase, IR and wave
solderable
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Maximum data rate: 50 MBaud
PACKAGES
CLK
RESB
DAT
GND
1
2
3
4
8 VDD
7 N/C
6 TXB
5 TX
3D3521M DIP (.300)
3D3521H Gull Wing (.300)
3D3521Z SOIC (.150)
CLK 1 14 VDD
N/C 2 13 N/C
N/C 3 12 N/C
RESB 4 11 N/C
DAT 5 10 N/C
N/C 6 9 TXB
GND 7 8 TX
3D3521 DIP (.300)
3D3521G Gull Wing (.300)
3D3521D SOIC (.150)
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3521 is a monolithic CMOS Manchester Encoder. The clock
and data, present at the unit input, are combined into a single bi-phase-
level signal. In this encoding mode, a logic one is represented by a
high-to-low transition within the bit cell, while a logic zero is represented
by a low-to-high transition. The unit operating baud rate (in Mbaud) is
equal to the input clock frequency (in MHZ). All pins marked N/C must
be left unconnected.
DAT
CLK
RESB
TX
TXB
VDD
GND
Data Input
Clock Input
Reset
Signal Output
Inverted Signal Output
+3.3 Volts
Ground
The all-CMOS 3D3521 integrated circuit has been designed as a reliable, economic alternative to hybrid
Manchester Encoders. It is CMOS-compatible and is offered in standard 8-pin and 14-pin auto-insertable
DIPs and space saving surface mount 8-pin and 14-pin SOICs.
Doc #06004
5/8/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D3521
APPLICATION NOTES
The 3D3521 Manchester Encoder samples the
data input at the rising edge of the input clock.
The sampled data is used in conjunction with the
clock rising and falling edges to generate the by-
phase level Manchester code.
INPUT SIGNAL CHARACTERISTICS
The 3D3521 Manchester Encoder inputs are
CMOS compatible. The user should assure
himself that the 50% (of VDD) threshold is used
when referring to all timing, especially to the input
clock duty cycle.
CLOCK DUTY CYCLE ERRORS
The 3D3521 Manchester Encoder employs the
timing of the clock rising and falling edges (duty
cycle) to implement the required coding scheme.
To reduce the difference between the output data
high time and low time, it is essential that the
deviation of the input clock duty cycle from 50/50
be minimized.
OUTPUT SIGNAL CHARACTERISTICS
The 3D3521 presents at its outputs the true and
the complimented encoded data.
The High-to-Low time skew of the selected data
output should be budgeted by the user, as it
relates to his application, to satisfactorily
estimate the distortion of the transmitted data
stream.
Such an estimate is very useful in determining
the
functionality and margins of the data link, if a
3D3522 Manchester Decoder is used to decode
the received data.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry is strongly dependent
on power supply and temperature. The
monolithic 3D3521 Manchester encoder utilizes
novel and innovative compensation circuitry to
minimize timing variations induced by fluctuations
in power supply and/or temperature.
RESET
(RESB)
CLOCK
(CIN)
DATA
(DIN)
tDS
TRANSMIT
(TXB)
TRANSMIT
(TX)
1/fC
1
0
tDH
Power-on reset (Left high for normal operation)
11001
0
T2H T2L
T1H T1L
1011001
Figure 1: Timing Diagram
0
Doc #06004
5/8/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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