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PDF U6101B Data sheet ( Hoja de datos )
| Número de pieza | U6101B | |
| Descripción | IF System and I/Q Demodulator | |
| Fabricantes | TEMIC Semiconductors | |
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U6101B
IF System and I/Q Demodulator for Digital Satellite
TV Transmissions
Description
The U6101B is a monolithic integrated circuit in
TEMIC’s UHF 5 technology for Satellite Digital Video
Broadcasting (DVBS) and other digital direct satellite
service applications. The circuit operates in a wide
frequency range and in a large input level range.
Implemented are two orthogonal mixer stages (precise
phase-matched by a control loop), a gain-controlled IF
amplifier of high input sensitivity with two switchable
isolated inputs, and an AGC-system for tuner and IF level
control. Alternatively the output level may be controlled
automatically, e.g., via the channel decoder AGC signal
output.
The local oscillator operates at IF input frequency. The
oscillator signal is internally doubled and divided again
to generate the orthogonal mixer driving signals.
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Features
D Frequency range from 390 to 520 MHz
D Two unbalanced switchable inputs
D High I/Q phase accuracy, based on TEMIC’s patented
0°/90° control loop circuit
D Input impedance 50 Ω, gain independent
D High input sensitivity
D AGC control range –35 dB
D Internal AGC detector
D Additionally external gain control and output level
setting possible
Benefits
D Two switchable IF-inputs to connect a combined
SAW filter
D Oscillator for SAW or LC tank circuit
D Adjustable tuner AGC control
D Low impedance output driver
D Balanced prescaler output
D Output signal level adjustable or fixed at typical or
minimum data sheet value by pin programming
D Low power consumption, 5-V supply voltage
Ordering Information
Extended Type Number
U6101B-AFSG3
Package
SSO20
Remarks
Taped and reeled
TELEFUNKEN Semiconductors
Rev. A1, 14-May-97
Preliminary Information
1 (7)
1 page  
U6101B
Functional Description
The input signal is via two single ended constant gain
amplifiers with selectable inputs connected to a gain
controlled amplifier. The differential output signal
*remains of constant amplitude to provide behind
*splitting up optimised dynamic operation points for a
pair of identical mixers. The mixer stages are driven by
two orthogonal oscillator signals, to generate the I- and Q-
components.
The oscillator operates at IF-frequency. Therefore control
by an on the shelf SAW resonator is possible. Using the
internal 1/32 frequency divider circuit a VCO carrier
recovery loop can be closed via the base band decoding
system.
Excellent accuracy of 0°/90° phase shifting between the
demodulator switching carriers is provided by a TEMIC
patented phase correction circuit, which operates in a
wide input frequency range.
Two matched amplifiers with second order lowpass
characteristic to suppress oscillator spurious ensure small
gain and phase errors between both channels and mini-
mize tilt. The output stages may drive complex loads up
to 220 Ω in series to 2.2 kΩ and 50 pF in a frequency
range up to 40 MHz.
To avoid fast system lock in time and driving the A/D
converters with defined output levels, in one channel the
output signal will be peak-level detected and in an
internally loop level controlled. So the output signal
amplitudes are independent of frequency and
characteristic of the QPSK modulation. The output level
can be set via an external potentiometer (or at two fixed
levels by pin programming) according the actual
application. External loop control by a channel decoder
generated AGC signal is provided.
The DC-component of the AGC loop affects the IF input
level. This signal is internally compared with a adjustable
threshold and generates a tuner AGC signal.
Small tolerances based on high DC operation point
stability and good spurious signal suppression are
performed by an internal reference voltage source.
Basic Application Circuit
4.7 W
10 nF
10 nF
+5 V
1 nF
Tuner
2.2 pF
22 nH
100 pF
3
2
19 1
Bias
circuit
100 pF 4
9
17
18 B 32
10 pF
14
15 VCO
10 pF
16
f → 2f
100 pF
20 12
Divider +
90° control
SW 2
+5 V
13
12608
100 nF
11
A/D
8
10
A/D
100 nF
7
6 100 nF
5
Figure 3. Internal AGC loop, output level optional changeable 0.6 Vpp to 1 Vpp
by control voltage at Pin 13, VCO carrier recovery
Channel
decoder
TELEFUNKEN Semiconductors
Rev. A1, 14-May-97
Preliminary Information
5 (7)
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet U6101B.PDF ] | |
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