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PDF X9400 Data sheet ( Hoja de datos )
| Número de pieza | X9400 | |
| Descripción | Quad Digitally Controlled Potentiometers | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
X9400
Low Noise/Low Power/SPI Bus
July 28, 2006
FN8189.3
Quad Digitally Controlled Potentiometers
(XDCP™)
FEATURES
• Four potentiometers per package
• 64 resistor taps
• SPI serial interface for write, read, and transfer
operations of the potentiometer
• Wiper resistance, 40Ω typical at 5V.
• Four non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on
power-up.
• Standby current < 1µA max
•
•
System
Analog
VV+C/VC:–:2-.75VV
to
to
5.5V
+5V
operation
• 10kΩ, 2.5kΩ end to end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per
register
• Low power CMOS
• 24 Ld SOIC and 24 Ld TSSOP
•www.DataSheet4U.com Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9400 integrates four digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0-3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power-up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
VSS
V+
V-
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
8
Data
R0 R1
R2 R3
Pot 0
Wiper
Counter
Register
(WCR)
VH0/RH0
VL0/RL0
VW0/RW0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW2/RW2
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VW1/RW1
Resistor
Array
Pot 1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VW3/RW3
Resistor
Array
Pot 3
VH3/RH3
VL3/RL3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X9400
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
From Interface
Circuitry
Register 0
8
Register 2
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
Register 1
6
Register 3
Serial
Bus
Input
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
UP/DN
Modified SCL
INC/DEC
Logic
UP/DN
CLK
C
o
u
n
t
e
r
D
e
c
o
d
e
VH/RH
VL/RL
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9400 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9400 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0 - A1 input
pins. The X9400 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9400 to successfully
VW/RW
continue the command sequence. The A0 - A1 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
The remaining two bits in the slave byte must be set to 0.
Figure 2. Identification Byte Format
Device Type
Identifier
0 1 0 1 0 0 A1 A0
Device Address
Instruction Byte
The next byte sent to the X9400 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
5 FN8189.3
July 28, 2006
5 Page 
X9400
ABSOLUTE MAXIMUM RATINGS
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SCK, SCL or any address
input with respect to VSS......................... -1V to +7V
Voltage on V+ (referenced to VSS)........................ 10V
Voltage on V- (referenced to VSS)........................-10V
(V+) - (V-) .............................................................. 12V
Any VH ....................................................................V+
Any VL ......................................................................V-
Lead temperature (soldering, 10 seconds) ........ 300°C
IW (10 seconds)................................................±12mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Device
X9400
X9400-2.7
Supply Voltage (VCC) Limits
5V ± 10%
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
RTOTAL
IW
RW
Parameter
End to end resistance
Power rating
Wiper current
Wiper resistance
Vv+
Vv-
VTERM
CH/CL/CW
IAL
Voltage on V+ Pin X9400
X9400-2.7
Voltage on V- Pin X9400
X9400-2.7
Voltage on any VH/RH or VL/RL Pin
Noise
Resolution
Absolute linearity (1)
Relative linearity (2)
Temperature coefficient of RTOTAL
Ratiometric temp. coefficient
Potentiometer capacitances
RH, RL, RW leakage current
Min.
+4.5
+2.7
-5.5
-5.5
V-
-1
-0.2
Limits
Typ. Max.
±20
50
±6
150 250
40 100
-120
1.6
±300
10/10/25
0.1
+5.5
+5.5
-4.5
-2.7
V+
+1
+0.2
±20
10
Unit
%
mW
mA
Ω
Ω
V
Test Conditions
25°C, each pot
Wiper Current = ± 1mA,
VCC = 3V
Wiper Current = ± 1mA,
VCC = 5V
V
V
dBV
%
MI(3)
MI(3)
ppm/°C
ppm/°C
pF
µA
Ref: 1kHz
Rw(n)(actual) - Rw(n)(expected)
Rw(n + 1) - [Rw(n) + MI]
See Spice Macromodel
VIN = VSS to VCC. Device is in
stand-by mode.
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when
used as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH - RL)/63, single pot
11 FN8189.3
July 28, 2006
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet X9400.PDF ] | |
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