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Fairchild Semiconductor |
December 2006
FIN12AC
µSerDes™ Low-Voltage 12-Bit Bi-Directional
Serializer/Deserializer with Multiple Frequency Ranges
tm
Features
■ Low power consumption
■ Fairchild proprietary low-power CTL interface
■ LVCMOS parallel I/O interface:
– 2mA source / sink current
– Over-voltage tolerant control signals
■ Parallel I/O power supply (VDDP) range between
1.65V and 3.6V
■ Analog power supply range of 2.5V to 3.05V
■ Multi-mode operation allows for a single device to
operate as Serializer or Deserializer
■ Internal PLL with no external components
■ Standby power-down mode support
■ Small footprint packaging:
– 32-terminal MLP and 42-ball BGA
■ Built-in differential termination
■ Supports external CKREF frequencies; 5MHz to 40MHz
■ Serialized data rate up to 560Mb/s
■ Voltage translation from 1.65V to 3.6V
Applications
■ Microcontroller or pixel interfaces
■ Image sensors
■ Small displays: LCD, cell phone, digital camera,
portable gaming, printer, PDA, video camera,
automotive
Description
The FIN12AC is a 12-bit serializer capable of running a
parallel frequency range between 5MHz and 40MHz.
The frequency range is selected by the S1 and S2 con-
trol signals. The bi-directional data flow is controlled
through use of a direction (DIRI) control pin. The devices
can be configured to operate in a unidirectional mode
only by hardwiring the DIRI pin. An internal Phase-
Locked Loop (PLL) generates the required bit clock fre-
quency for transfer across the serial link. Options exist
for dual or single PLL operation, dependent upon system
operational parameters. The device has been designed
for low power operation and utilizes Fairchild proprietary
low-power control Current Transistor Logic (CTL) inter-
face. The device also supports an ultra low power power-
down mode for conserving power in battery-operated
applications.
Ordering Information
Part Number
Package
FIN12ACGFX 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA),
JEDEC MO-195, 3.5mm Wide
FIN12ACMLX 32-Terminal Molded Leadless Package (MLP),
Quad, JEDEC MO-220, 5mm Square
Pb-Free
Yes
Yes
Operating
Temperature
Range
Packing
Method
-30°C to +70°C Tape and Reel
-30°C to +70°C Tape and Reel
µSerDesTM is a trademark of Fairchild Semiconductor Corporation.
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.0
www.fairchildsemi.com
Functional Block Diagram
CKREF
PLL
0
PLLx_SEL
STROBE
DP[1:12]
CKP
S1
S2
DIRI
diri_int
cksint
I
Word
Boundary
Generator
I
0
Serializer
Control
+
-
diri_int
Serializer
+
-
CKS0+
CKS0-
DSO+/DSI-
DSO-/DSI+
Deserializer
+ 100 Gated
- Termination
Deserializer
Control
cksint
+
-
CKSI+
CKSI-
I
100 Gated
0
WORD CK
Termination
Generator
Control Logic
Freq Direction
Control Control
DIRO
Power Down Control
Figure 1. FIN12AC Block Diagram
Connection Diagrams
Terminal Assignments for MLP
DP[4]
DP[5]
DP[6]
VDDP
CKP
DP[7]
DP[8]
DP[9]
1
2
3
4
5
6
7
8
24 CKSO+
23 CKSO-
22 DSO+/DSI-
21 DSO-/DSI+
20 CKSI-
19 CKSI+
18 DIRI
17 VDDS
Pin Assignments for BGA
123456
A
B
C
D
E
F
G
(Top View)
(Top View)
Figure 2. Terminal and Pin Assignments
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.0
2
www.fairchildsemi.com
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