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PDF X40420 Data sheet ( Hoja de datos )
| Número de pieza | X40420 | |
| Descripción | (X40420 / X40421) Dual Voltage Monitor | |
| Fabricantes | Xicor | |
| Logotipo |  |
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New Features
• Monitor Voltages: 5V to 1.6V
• Memory Security
• Battery Switch Backup
• VOUT 5mA to 50mA
Preliminary Datasheet
4kbit EEPROM
X40420/X40421
Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch
FEATURES
• Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
—VTRIP2 Programmable down to 0.9V
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor two voltages or detect power fail
• Battery Switch Backup
• VOUT: 5mA to 50mA from VCC; or 250µA from
VBATT
• Fault detection register
• Selectable power on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA typical battery current in backup mode
•www.DataSheet4U.com 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0 or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
APPLICATIONS
• Communications Equipment
—Routers, Hubs, Switches
—Disk arrays
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Desktop Computers
—Network Servers
X40420/21
Standard VTRIP1 Level Standard VTRIP2 Level
4.6V (+/-1%)
2.9V(+/-1.7%)
4.6V (+/-1%)
2.6V (+/-2%)
2.9V(+/-1.7%)
1.6V (+/-3%)
See “Ordering Information” for more details
For Custom Settings, call Xicor.
Suffix
-A
-B
-C
DESCRIPTION
The X40420/21 combines power-on reset control,
watchdog timer, supply voltage supervision, and sec-
ondary supervision, manual reset, and Block Lock™
protect serial EEPROM in one package. This combina-
tion lowers system cost, reduces board space require-
ments, and increases reliability.
Applying voltage to VCC activates the power on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
BLOCK DIAGRAM
V2MON
SDA
WP
SCL
VCC
(V1MON)
BATT-ON
VOUT
VBATT
REV 1.2.14 7/12/02
Data
Register
Command
Decode Test
& Control
Logic
System
Battery
Switch
V2 Monitor
Logic
VOUT
+
VTRIP2
-
Fault Detection
Register
Status
Register
EEPROM
Array
VCCLoMgoicnitor
VOUT
+
VTRIP1
-
Watchdog
and
Reset Logic
Power on,
Manual Reset
Low Voltage
Reset
Generation
VOUT
V2FAIL
WDO
MR
RESET
X40420
RESET
X40421
LOWLINE
www.xicor.com
Characteristics subject to change without notice. 1 of 25
1 page  
X40420/X40421 – Preliminary
Figure 3. VTRIPX Set/Reset Conditions
VTRIPX
(X = 1, 2)
WDO
VCC/V2MON
VP
SCL
0
70
70
7
SDA
A0h
00h tWC
Figure 4. Watchdog Restart
.6µs
SCL
1.3µs
Data Byte in order to program VTRIPx. The STOP bit
following a valid write operation initiates the programming
sequence. Pin WDO must then be brought LOW to
complete the operation.
SDA
Start
WDT Reset Stop
V1 AND V2 THRESHOLD PROGRAM PROCEDURE
(OPTIONAL)
The X40420/21 is shipped with standard V1 and V2
threshold (VTRIP1, VTRIP2) voltages. These values will not
change over normal operating and storage conditions.
However, in applications where the standard thresholds
are not exactly right, or if higher precision is needed in the
threshold value, the X40420 trip points may be adjusted.
The procedure is described below, and uses the applica-
tion of a high voltage control signal.
Setting a VTRIPx Voltage (x=1, 2)
There are two procedures used to set the threshold volt-
ages (VTRIPx), depending if the threshold voltage to be
stored is higher or lower than the present value. For
example, if the present VTRIPx is 2.9 V and the new
VTRIPx is 3.2 V, the new voltage can be stored directly
into the VTRIPx cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the VTRIPx voltage before setting the new value.
Setting a Higher VTRIPx Voltage (x=1, 2)
To set a VTRIPx threshold to a new voltage which is higher
than the present threshold, the user must apply the
desired VTRIPx threshold voltage to the corresponding
input pin (Vcc(V1MON) or V2MON). Then, a program-
ming voltage (Vp) must be applied to the WDO pin before
a START condition is set up on SDA. Next, issue on the
SDA pin the Slave Address A0h, followed by the Byte
Address 01h for VTRIP1, and 09h for VTRIP2, and a 00h
To check if the VTRIPX has been set, set VXMON to a
value slightly greater than VTRIPX (that was previously
set). Slowly ramp down VXMON and observe when the
corresponding outputs (LOWLINE and V2FAIL) switch.
The voltage at which this occurs is the VTRIPX (actual).
CASE A
Now if the desired VTRIPX is greater than the VTRIPX
(actual), then add the difference between VTRIPX
(desired) – VTRIPX (actual) to the original VTRIPX desired.
This is your new VTRIPX that should be applied to
VXMON and the whole sequence should be repeated
again (see Figure 5).
CASE B
Now if the VTRIPX (actual), is higher than the VTRIPX
(desired), perform the reset sequence as described in the
next section. The new VTRIPX voltage to be applied to
VXMON will now be: VTRIPX (desired) – (VTRIPX (actual)
– VTRIPX (desired)).
Note: 1. This operation does not corrupt the memory
array.
2. Set VCC = 5V, when VTRIP2 is being pro-
grammed
Setting a Lower VTRIPx Voltage (x=1, 2)
In order to set VTRIPx to a lower voltage than the
present value, then VTRIPx must first be “reset” accord-
ing to the procedure described below. Once VTRIPx
has been “reset”, then VTRIPx can be set to the desired
voltage using the procedure described in “Setting a
Higher VTRIPx Voltage”.
REV 1.2.14 7/12/02
www.xicor.com
Characteristics subject to change without notice. 5 of 25
5 Page 
X40420/X40421 – Preliminary
Figure 10. Byte Write Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
Slave
Address
t
Byte
Address
0
AA
CC
KK
Data
S
t
o
p
A
C
K
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page.
This means that the master can write 16 bytes to the
page starting at any location on that page. If the mas-
ter begins writing at location 10, and loads 12 bytes,
then the first 6 bytes are written to locations 10 through
15, and the last 6 bytes are written to locations 0
through 5. Afterwards, the address counter would point
to location 6 of the page that was just written. If the
master supplies more than 16 bytes of data, then new
data over-writes the previous data, one byte at a time.
Figure 11. Page Write Operation
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
Slave
Address
r
t
101 00 0
A
C
K
Byte
Address
A
C
K
Data
(1)
(1 ≤ n ≤ 16)
Data
(n)
A
C
K
S
t
o
p
A
C
K
Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.
6 Bytes
6 Bytes
address
=5
address pointer
ends here
Addr = 6
address
10
address
n-1
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 11 for the address, acknowl-
edge, and data transfer sequence.
REV 1.2.14 7/12/02
www.xicor.com
Characteristics subject to change without notice. 11 of 25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet X40420.PDF ] | |
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