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PDF ISL22316 Data sheet ( Hoja de datos )
| Número de pieza | ISL22316 | |
| Descripción | Single Digitally Controlled Potentiometer | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
ISL22316
Single Digitally Controlled Potentiometer (XDCP™)
August 14, 2015
FN6186.3
Low Noise, Low Power I2C™ Bus,
128 Taps
The ISL22316 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up, the device recalls the contents of the
DCP’s IVR to the WR.
The DCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Pinouts
SCL
SDA
A1
A0
SHDN
ISL22316
(10 LD MSOP)
TOP VIEW
1 10
29
38
47
56
VCC
RH
RW
RL
GND
Features
• 128 resistor taps
• I2C serial interface
- Two address pins, up to four devices/bus
• Non-volatile storage of wiper position
• Wiper resistance: 70 typical @ VCC = 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kor 10k total resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T +55°C
• 10 Ld MSOP or 10 Ld TDFN package
• Pb-free (RoHS compliant)
ISL22316
(10 LD TDFN)
TOP VIEW
SCL 1 O
SDA 2
A1 3
A0 4
SHDN 5
10 VCC
9 RH
8 RW
7 RL
6 GND
Ordering Information
PART NUMBER
(Note)
PART
MARKING
RESISTANCE OPTION
(k)
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG. DWG. #
ISL22316UFU10Z*
(No longer available,
recommended
replacement:
(ISL22316WFRT10Z-TK)
316UZ
50
-40 to +125
10 Ld MSOP
M10.118
ISL22316WFU10Z*
316WZ
10
-40 to +125
10 Ld MSOP
M10.118
ISL22316UFRT10Z*
(No longer available,
recommended
replacement:
(ISL22316WFRT10Z-TK)
316U
50
-40 to +125
10 Ld 3x3 TDFN
L10.3x3B
ISL22316WFRT10Z*
316W
10
-40 to +125
10 Ld 3x3 TDFN
L10.3x3B
*Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2006, 2008, 2009, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL22316
Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN TYP MAX
(Note 19) (Note 5) (Note 19) UNIT
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
Cycles
EEPROM Retention
Temperature T +55°C
50
Years
tWC Non-volatile Write Cycle Time
(Note 17)
12 20 ms
SERIAL INTERFACE SPECIFICATIONS
VIL A1, A0, SHDN, SDA, and SCL Input Buffer
LOW Voltage
-0.3
0.3*VCC
V
VIH A1, A0, SHDN, SDA, and SCL Input Buffer
HIGH Voltage
0.7*VCC
VCC + 0.3 V
Hysteresis SDA and SCL Input Buffer Hysteresis
VOL SDA Output Buffer LOW Voltage, Sinking
4mA
0.05*VCC
0
V
0.4 V
Cpin A1, A0, SHDN, SDA, and SCL Pin
(Note 18) Capacitance
10 pF
fSCL
tsp
SCL Frequency
Pulse Width Suppression Time at SDA and Any pulse narrower than the max spec is
SCL Inputs
suppressed
400 kHz
50 ns
tAA
tBUF
SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window
Time the Bus Must be Free Before the Start SDA crossing 70% of VCC during a STOP
of a New Transmission
condition, to SDA crossing 70% of VCC
during the following START condition
1300
900 ns
ns
tLOW
tHIGH
tSU:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
Measured at the 30% of VCC crossing
Measured at the 70% of VCC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
1300
600
600
600
100
0
ns
ns
ns
ns
ns
ns
tSU:STO STOP Condition Setup Time
tHD:STO
tDH
STOP Condition Hold Time for Read, or
Volatile Only Write
Output Data Hold Time
tR SDA and SCL Rise Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
From SDA rising edge to SCL falling edge;
both crossing 70% of VCC
From SCL falling edge crossing 30% of
VCC, until SDA enters the 30% to 70% of
VCC window
From 30% to 70% of VCC
600
1300
0
20 +
0.1*Cb
ns
ns
ns
250 ns
tF SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1*Cb
250 ns
Cb Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10 400 pF
5 FN6186.3
August 14, 2015
5 Page 
ISL22316
non-volatile register (IVR) at address 0, contain initial wiper
position and volatile registers (WR) contain current wiper
position.
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
2—
ACR
1 Reserved
0 IVR
WR
The non-volatile IVR and volatile WR registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described in Table 2.
The VOL bit (ACR<7>) determines whether the access is to
wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
VOL
SHDN WIP
0
0
0
0
0
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.
The SHDN bit (ACR<6>) disables or enables Shutdown mode.
This bit is logically AND with SHDN pin. When this bit is 0, DCP
is in Shutdown mode. Default value of SHDN bit is 1.
The WIP bit (ACR<5>) is read only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the WR or ACR while WIP bit is 1.
Shutdown Mode
The device can be put in Shutdown mode either by pulling the
SHDN pin to GND or setting the SHDN bit in the ACR register
to 0. The truth table for Shutdown mode is in Table 3.
TABLE 3.
SHDN pin
SHDN bit
Mode
High
1 Normal operation
Low 1
Shutdown
High
0
Shutdown
Low 0
Shutdown
I2C Serial Interface
The ISL22316 supports an I2C bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22316
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions
(see Figure 16). On power-up of the ISL22316, the SDA pin
is in the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22316 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 16). A START condition is ignored during the
power-up of the device.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 17).
The ISL22316 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22316 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present
at pins A1 and A0. The LSB is the Read/Write bit. Its value is
“1” for a Read operation, and “0” for a Write operation
(see Table 4).
Logic values at pins A1 and A0 respectively
0
(MSB)
1 0 1 0 A1 A0
TABLE 4. IDENTIFICATION BYTE FORMAT
R/W
(LSB)
11 FN6186.3
August 14, 2015
11 Page | ||
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| PDF Descargar | [ Datasheet ISL22316.PDF ] | |
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