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PDF ADF4360-1 Data sheet ( Hoja de datos )
| Número de pieza | ADF4360-1 | |
| Descripción | Integrated Synthesizer and VCO | |
| Fabricantes | Analog Devices | |
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Data Sheet
Integrated Synthesizer and VCO
ADF4360-1
FEATURES
GENERAL DESCRIPTION
Output frequency range: 2050 MHz to 2450 MHz
Divide-by-2 output
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 8/9, 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
The ADF4360-1 is a fully integrated integer-N synthesizer and
voltage-controlled oscillator (VCO). The ADF4360-1 is
designed for a center frequency of 2250 MHz. In addition, there
is a divide-by-2 option available, whereby the user gets an RF
output of between 1025 MHz and 1225 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
APPLICATIONS
Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
CE RSET
REFIN
CLK
DATA
LE
ADF4360-1
14-BIT R
COUNTER
24-BIT
DATA REGISTER
24-BIT
FUNCTION
LATCH
LOCK
DETECT
MULTIPLEXER
MUTE
CHARGE
PUMP
PHASE
COMPARATOR
MUXOUT
CP
VVCO
VTUNE
CC
CN
INTEGER
REGISTER
PRESCALER
P/P+1
N = (BP + A)
13-BIT B
COUNTER
LOAD
LOAD
5-BIT A
COUNTER
VCO
CORE
DIVSEL = 1
OUTPUT
STAGE
RFOUTA
RFOUTB
÷2
AGND
DIVSEL = 2
DGND
CPGND
Figure 1.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no re-
sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADF4360-1
Data Sheet
Parameter
NOISE CHARACTERISTICS1, 5
VCO Phase-Noise Performance8
Synthesizer Phase-Noise Floor9
In-Band Phase Noise10, 11
RMS Integrated Phase Error12
Spurious Signals due to PFD Frequency11, 13
Level of Unlocked Signal with MTLD Enabled
B Version
−110
−130
−141
−148
−172
−163
−147
−81
0.72
−70
−38
Unit
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Degrees typ
dBc typ
dBm typ
Test Conditions/Comments
At 100 kHz offset from carrier.
At 1 MHz offset from carrier.
At 3 MHz offset from carrier.
At 10 MHz offset from carrier.
At 25 kHz PFD frequency.
At 200 kHz PFD frequency.
At 8 MHz PFD frequency.
At 1 kHz offset from carrier.
100 Hz to 100 kHz.
1 Operating temperature range is –40°C to +85°C.
2 Guaranteed by design. Sample tested to ensure compliance.
3 ICP is internally modified to maintain constant-loop gain over the frequency range.
4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; P = 32.
5 These characteristics are guaranteed for VCO Core Power = 15 mA.
6 Jumping from 2.05 GHz to 2.45 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7 Using 50 Ω resistors to VVCO into a 50 Ω load. For tuned loads, see the Output Matching section.
8 The noise of the VCO is measured in open-loop conditions.
9 The synthesizer phase-noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value).
10 The phase noise is measured with the EV-ADF4360-1EB1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the
synthesizer; offset frequency = 1 kHz.
11 fREFIN = 10 MHz; fPFD = 200 kHz; N = 12500; loop bandwidth = 10 kHz.
12 fREFIN = 10 MHz; fPFD = 1 MHz; N = 2400; loop bandwidth = 25 kHz.
13 The spurious signals are measured with the EV-ADF4360-1EB1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for
the synthesizer; fREFOUT = 10 MHz at 0 dBm.
Rev. D | Page 4 of 24
5 Page 
ADF4360-1
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360-1 allows the user to
access various internal points on the chip. The state of MUX-
OUT is controlled by M3, M2, and M1 in the function latch.
The full truth table is shown in Table 7. Figure 13 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. When LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error greater than 25 ns is detected on any subse-
quent PD cycle.
The N-channel open-drain analog lock detect should be operat-
ed with an external pull-up resistor of 10 kΩ nominal. When
lock has been detected, the output is high with narrow low-
going pulses.
DVDD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUX
CONTROL
MUXOUT
DGND
Figure 13. MUXOUT Circuit
INPUT SHIFT REGISTER
The digital section of the ADF4360-1 includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter, com-
prising of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs are DB1 and
DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test mode latch is used for factory testing and should not be
programmed by the user.
Data Sheet
Table 5. C2 and C1 Truth Table
Control Bits
C2 C1 Data Latch
0 0 Control Latch
0 1 R Counter
1 0 N Counter (A and B)
1 1 Test Mode Latch
VCO
The VCO core in the ADF4360-1 uses eight overlapping bands,
as shown in Figure 14, to allow a wide frequency range to be
covered without a large VCO sensitivity (KV) and resultant poor
phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at power-
up. This sequence is
1. R counter latch
2. Control latch
3. N counter latch
During band select, which takes five PFD cycles, the VCO VTUNE
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
FREQUENCY (MHz)
Figure 14. Frequency vs. VTUNE, ADF4360-1
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8
and is controlled by Bits BSC1 and BSC2 in the R counter latch.
Where the required PFD frequency exceeds 1 MHz, the divide
ratio should be set to allow enough time for correct band
selection.
Rev. D | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ADF4360-1.PDF ] | |
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