파트넘버.co.kr WM8195 데이터시트 PDF


WM8195 반도체 회로 부품 판매점

14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser



Wolfson Microelectronics 로고
Wolfson Microelectronics
WM8195 데이터시트, 핀배열, 회로
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WM8195
14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser
DESCRIPTION
FEATURES
The WM8195 is a 14-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 12MSPS.
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset Adjust functions. Three multiplexers allow single
channel processing. The output from each of these
channels is time multiplexed into a single high-speed 14-bit
analogue-to-digital converter. The digital output data is
available in 14-bit parallel or 8, 7 or 4-bit wide multiplexed
format, with no missing codes.
14-bit ADC
No missing codes guaranteed
12MSPS conversion rate
Low power – 210mW typical
5V single supply or 5V/3.3V dual supply operation
Single or 3 channel operation
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
Programmable clamp voltage
14-bit parallel or 8, 7 or 4-bit wide multiplexed data output
formats
Internally generated voltage references
48-lead TQFP package
An internal 4-bit DAC is supplied for internal reference level
Serial or parallel control interface
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
APPLICATIONS
signals. Alternatively an external reference level may be
applied. ADC references are generated internally, ensuring
optimum performance from the device.
Flatbed and sheetfeed scanners
USB compatible scanners
Multi-function peripherals
Using an analogue supply voltage of 5V and a digital
High-performance CCD sensor interface
interface supply of either 5V or 3.3V, the WM8195 typically
only consumes 210mW when operating from a single 5V
www.DataSheet4U.com
supply and less than 20µA when in power down mode.
BLOCK DIAGRAM
VRLC/VBIAS
CL
RINP
RLC
GINP
RLC
VSMP MCLK
AVDD1-2
DVDD1-3
RS VS
M
U
X
TIMING CONTROL
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WM8195
CDS
RM
GU
X
B
8
OFFSET
DAC
VREF/BIAS
+ PGA
RM
GU
X
B
I/P SIGNAL
8 POLARITY
ADJUST
CDS
+ PGA
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
VRT VRX VRB
+
M
+U
X
14-
BIT
ADC
DATA
I/O
PORT
BINP
RLC
RLC
DAC 4
CDS
+ PGA
+
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
CONFIGURABLE
SERIAL/
PARALLEL
CONTROL
INTERFACE
OEB
OP[0]
OP[1]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]
OP[8]
OP[9]
OP[10]
OP[11]
OP[12]
OP[13]/SDO
SEN/STB
SCK/RNW
SDI/DNA
RLC/ACYC
NRESET
AGND1-6
DGND1-5
WOLFSON MICROELECTRONICS plc
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Production Data July 2005 Rev 4.1
Copyright 2005 Wolfson Microelectronics plc.


WM8195 데이터시트, 핀배열, 회로
WM8195
Production Data
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM .................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
PIN DESCRIPTION ................................................................................................4
ABSOLUTE MAXIMUM RATINGS.........................................................................6
RECOMMENDED OPERATING CONDITIONS .....................................................6
ELECTRICAL CHARACTERISTICS ......................................................................7
INPUT VIDEO SAMPLING............................................................................................... 9
OUTPUT DATA TIMING .................................................................................................. 9
SERIAL INTERFACE ..................................................................................................... 11
PARALLEL INTERFACE......................................................................................12
INTRODUCTION ........................................................................................................... 13
INPUT SAMPLING......................................................................................................... 13
RESET LEVEL CLAMPING (RLC) ................................................................................. 13
CDS/NON-CDS PROCESSING ..................................................................................... 14
OFFSET ADJUST AND PROGRAMMABLE GAIN......................................................... 15
ADC INPUT BLACK LEVEL ADJUST ............................................................................ 16
OVERALL SIGNAL FLOW SUMMARY .......................................................................... 16
CALCULATING OUTPUT FOR ANY GIVEN INPUT ...................................................... 17
OUTPUT FORMATS...................................................................................................... 18
CONTROL INTERFACE ................................................................................................ 19
TIMING REQUIREMENTS............................................................................................. 20
PROGRAMMABLE VSMP DETECT CIRCUIT ............................................................... 21
REFERENCES............................................................................................................... 21
POWER SUPPLY .......................................................................................................... 22
POWER MANAGEMENT ............................................................................................... 22
LINE-BY-LINE OPERATION .......................................................................................... 22
OPERATING MODES .................................................................................................... 24
OPERATING MODE TIMING DIAGRAMS ..................................................................... 25
DEVICE CONFIGURATION .................................................................................27
REGISTER MAP ............................................................................................................ 27
REGISTER MAP DESCRIPTION................................................................................... 28
RECOMMENDED EXTERNAL COMPONENTS ..................................................31
PACKAGE DIMENSIONS ....................................................................................32
IMPORTANT NOTICE ..........................................................................................33
ADDRESS:..................................................................................................................... 33
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PD Rev 4.1 July 2005
2




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