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NJ88C50 반도체 회로 부품 판매점

Dual Low Power Frequency Synthesiser



Zarlink Semiconductor 로고
Zarlink Semiconductor
NJ88C50 데이터시트, 핀배열, 회로
www.DataSheet4U.com
NJ88C50
Dual Low Power Frequency Synthesiser
The NJ88C50 is a low power integrated circuit, designed
as the heart of a fast locking PLL subsystem in a mobile radio
application. It is manufactured on Mitel Semiconductor 1.4
micron double polysilicon CMOS process, which ensures that
low power and low noise performance is achieved. The device
contains two synthesisers, one for the generation of VHF
signals up to 125MHz and a second for UHF (when used with
a mulitmodulus prescaler such as the SP8713/14/15). The
main synthesiser has the capability of driving a dual speed
loop filter and also can perform Fractional-N interpolation.
Both synthesisers use current source outputs from their
phase detectors to minimise external components. Various
sections may be powered down for battery economy.
FEATURES
• 30MHz main synthesiser
• 125MHz auxiliary synthesiser
• Programmable output current
from phase detector - up to 10mA
• High input sensitivity
• Fractional-N interpolator
• Supports up to 4 modulus prescalers
• SSOP package
DS3805
ISSUE 1.8
Ordering Information
NJ88C50/MA/NP - (Industrial temp
range in SSOP package)
June 2002
AVDD
FIM
FIMB
DATA
CKIN
STROBE
RI
FIA
RSA
PDA
1 20
2 19
3 18
4 17
5 NJ88C50 16
6 15
7 14
8 13
9 12
10 11
AGND
MOD2
MOD1
SCREEN
RSC
RSM
VDD
PDP
GND
PDI
APPLICATIONS
• NMT, AMPS, ETACS cellular
• GSM, IS-54, RCR-27 cellular
• DCS1800 microcellular
• DLMR, DSRR, TETRA
• DECT, PHP cordless telephones
NP20
Figure 1 - Pin assignment
ABSOLUTE MAXIMUM RATINGS
Storage temperature
-55°C to +150°C
Operating temperature
-40°C to +85°C
Supply voltage
-0.5 to 7.0V
Voltage on any pin
-0.3V to (VDD + 0.3V)
FIM
FIMB
DATA
CKIN
STROBE
RI
FIA
MOD1
MOD2
MAIN N
BUFFER
SERIAL
INPUT
REGISTER
R BUFFER
AUX. N
BUFFER
MAIN N-DIVIDER
LATCH
LATCH
R DIVIDER
QBAR
Q
LATCH
AUX. N-DIVIDER
PHASE
DETECTOR
RSC RSM
CURRENT
SOURCE
PDI
PDP
LATCH
FRACTIONAL-N
SYSTEM
PHASE
DETECTOR
CURRENT
SOURCE
PDA
Figure 2 - Simplified block diagram
RSA


NJ88C50 데이터시트, 핀배열, 회로
NJ88C50
Architecture
Fig.2 shows a simplified block diagram of the NJ88C50, a
more detailed description of each block and its function is
given later in this datasheet.
The synthesiser consists of the following blocks
- 35MHz reference frequency input buffer
- 35MHz programmable reference divider
- 125MHz Auxiliary synthesiser input buffer
- 125MHz Auxiliary synthesiser programmable divider
- Auxiliary synthesiser phase detector with current source
outputs
- 30MHz main synthesiser input buffer (differential inputs)
- 30MHz main synthesiser programmable divider and control
logic
- Main synthesiser Fractional-N interpolation system
- Main synthesiser phase detector with dual current source
outputs
PIN Description
Pin Name
1 AVDD
2 FIM
3 FIMB
4 DATA
5 CKIN
6 STROBE
7 RI
8 FIA
9 RSA
10 PDA
11 PDI
12 GND
13 PDP
14 VDD
15 RSM
16 RSC
17 SCREEN
18 MOD1
19 MOD2
20 AGND
Function
Analog supply pin (nominally 5V).
Main synthesiser balanced input buffer, may be used with single ended prescaler output if Fimb
is biased.
Main synthesiser balanced input buffer, may be used with balanced prescaler output, or biased
for single ended operation.
Serial input for programming data.
Serial clock input for programming bus.
Program enable pin, active low.
Master reference frequency input, should be a.c coupled from an accurate source.
Auxiliary synthesiser frequency input, should be a.c coupled.
Current setting resistor connection defining auxiliary phase detector output current.
Tristate current output from auxiliary phase detector.
Tristate current output from the main synthesiser's phase detector giving integral control.
Digital ground supply pin.
Tristate current output from the main synthesiser's phase detector giving proportional control.
Digital supply pin (nominally 5V).
Current setting resistor connection defining main synthesiser's phase detector output currents.
Current setting resistor connection defining the compensation current for fractional-N ripple
elimination in the main synthesiser's current source outputs.
To be connected to ground to provide isolation of the modulus control pins from RF interference.
Modulus control pin (see truth table).
Modulus control pin (see truth table).
Analog ground supply pin.
It is recommended that power supply pins are well decoupled to minimise power rail born interference.
2




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