PDF 74FST6800 Data sheet ( Hoja de datos )

Número de pieza	74FST6800
Descripción	10-Bit Bus Switch
Fabricantes	ON Semiconductor
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No Preview Available ! www.DataSheet4U.com 74FST6800 10−Bit Bus Switch with Precharged Outputs The ON Semiconductor 74FST6800 is a 10−bit bus switch with precharged outputs. The device is CMOS TTL compatible when operating between 4.0 and 5.5 Volts. The device exhibits extremely low RON and adds nearly zero propagation delay. The device adds no noise or ground bounce to the system. Features • RON t 4 W Typical • Less Than 0.25 ns−Max Delay Through Switch • Nearly Zero Standby Current • No Circuit Bounce • Control Inputs are TTL/CMOS Compatible • Pin−For−Pin Compatible With QS6800, FST6800, CBT6800 • All Popular Packages: SOIC−24, TSSOP−24, QSOP−24 • All Devices in Package TSSOP are Inherently Pb−Free* OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BIASV Figure 1. 24−Lead Pinout http://onsemi.com 24 1 SOIC−24 DW SUFFIX CASE 751E MARKING DIAGRAMS 24 FST6800 AWLYWW 1 24 1 TSSOP−24 DT SUFFIX CASE 948H 24 FST 6800 ALYW 1 24 1 QSOP−24 QS SUFFIX CASE 492B 24 FST6800 AWLYYWW 1 TRUTH TABLE OE B0−B9 Function L A0−A9 Connect H Bias V Precharge NOTE: H = HIGH Voltage Level L = LOW Voltage Level A L, WL Y, YY W, WW = = = = Assembly Location Wafer Lot Year Work Week PIN NAMES Pin OE A B Description Bus Switch Enable Bus A Bus B *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 6 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Publication Order Number: 74FST6800/D 1 page 74FST6800 PACKAGE DIMENSIONS SOIC−24 D SUFFIX CASE 751E−04 ISSUE E −A− 24 13 1 −T− SEATING PLANE −B− 12X P 0.010 (0.25) M B M 12 24X D 0.010 (0.25) M T A S B S J F 22X G C M K R X 45 _ 0.15 (0.006) T U S TSSOP−24 DT SUFFIX CASE 948H−01 ISSUE A 24X K REF 0.10 (0.004) M T U S V S 2X L/2 L PIN 1 IDENT. 24 1 0.15 (0.006) T U S A −V− 13 B −U− 12 0.10 (0.004) −T− SEATING PLANE D C K K1 ÇÉÇÉÇJ1 ÇÉÇÉÇSECTION N−N J G N N F DETAIL E H 0.25 (0.010) M http://onsemi.com 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 15.25 15.54 0.601 0.612 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.41 0.90 0.016 0.035 G 1.27 BSC 0.050 BSC J 0.23 0.32 0.009 0.013 K 0.13 0.29 0.005 0.011 M 0_ 8_ 0_ 8_ P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 7.70 7.90 0.303 0.311 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ −W− DETAIL E 5 Page

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