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PDF ST62E32B Data sheet ( Hoja de datos )
| Número de pieza | ST62E32B | |
| Descripción | (ST62E32B / ST62T32B) 8-BIT OTP/EPROM MCUs | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST62T32B
ST62E32B
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
s -40 to +125°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 192 bytes
s Data EEPROM: 128 bytes
s User Programmable Options
s 30 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
s 9 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
s 8-bit Timer/ Counter with 7-bit programmable
prescaler
s 16-bit Auto-reload Timer with 7-bit
programmable prescaler (AR Timer)
s Digital Watchdog
s 8-bit A/D Converter with 21 analog inputs
s 8-bit Synchronous Peripheral Interface (SPI)
s 8-bit Asynchronous Peripheral Interface
(UART)
s On-chip Clock oscillator can be driven by Quartz
Crystal or Ceramic resonator
s Oscillator Safe Guard
s One external Non-Maskable Interrupt
s ST623x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
DEVICE
ST62T32B
ST62E32B
OTP
(Bytes)
7948
EPROM
(Bytes)
-
7948
I/O Pins
30
30
September 1998
PSDIP42
PQFP52
CDIP42W
(See end of Datasheet for Ordering Information)
Rev. 2.5
1/86
105
1 page  
ST62T32B ST62E32B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T32B and ST62E32B devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which is targeted at low to me-
dium complexity applications. All ST62xx devices
are based on a building block approach: a com-
Figure 1. Block Diagram
mon core is surrounded by a number of on-chip
peripherals.
The ST62E32B is the erasable EPROM version of
the ST62T32B device, which may be used to em-
ulate the ST62T32B device, as well as the respec-
tive ST6232B ROM devices.
TEST/VPP
NMI
TEST
8-BIT
A/D CONVERTE R
INTERRUP T
PROGR AM
Memory
7948 bytes
DATA ROM
USER
SELECTA BLE
DATA RAM
192 Bytes
DATA EEPROM
128 Bytes
PORT A
PORT B
PORT C
PORT D
UART
PORT E
PA0..PA1 / 20 mA Sink
PA2/OVF / 20 mA Sink
PA3/PWM/20 mA Sink
PA4/Ain/CP1
PA5/A in/CP2
PA6.. .PA7/Ain
PB0/Ain
P B3..PB7 /Ain
PC5..PC7/Ain
PD0,PD6,PD7/Ain
PD1/Ain/Scl
PD2/Ain/Sin
PD3/Ain/Sout
P D4/Ain/RX D1
P D5/Ain/T XD1
PE0...PE4
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8 BIT CORE
POWER
SUPP LY
OSCILLATOR
RESET
A UTORELOA D
TIMER
TIMER
SPI (SERIAL
PE RIPHERAL
INTERFAC E)
DIGITAL
WATCHDOG
TIMER
VDD VSS OSCin OSCout RESET
(VPP on EPROM/OT P versions only)
VR01823E
5/86
109
5 Page 
ST62T32B ST62E32B
MEMORY MAP (Cont’d)
1.3.5 Data Window Register (DWR)
Data Window Register (DWR)
The Data read-only memory window is located from
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes locat-
ed anywhere in program memory, between ad-
dress 0000h and 1FFFh (top memory address de-
pends on the specific device). All the program
memory can therefore be used to store either in-
structions or read-only data. Indeed, the window
can be moved in steps of 64 bytes along the pro-
gram memory by writing the appropriate code in the
Data Window Register (DWR).
The DWR can be addressed like any RAM location
in the Data Space, it is however a write-only regis-
ter and therefore cannot be accessed using single-
bit operations. This register is used to position the
64-byte read-only data window (from address 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte to be read as data in program memory is
obtained by concatenating the 6 least significant
bits of the register address given in the instruction
(as least significant bits) and the content of the
DWR register (as most significant bits), as illustrat-
ed in Figure 6 below. For instance, when address-
ing location 0040h of the Data Space, with 0 load-
ed in the DWR register, the physical location ad-
dressed in program memory is 00h. The DWR reg-
ister is not cleared on reset, therefore it must be
written to prior to the first access to the Data read-
only memory window area.
Address: 0C9h — Write Only
70
- DWR6 DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
Bits 7 = Not used.
Bit 6-0 = DWR5-DWR0: Data read-only memory
Window Register Bits. These are the Data read-
only memory Window bits that correspond to the
upper bits of the data read-only memory space.
Caution: This register is undefined on reset. Nei-
ther read nor single bit instructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while exe-
cuting an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossible to avoid writ-
ing to the DWR during the interrupt service routine,
an image of the register must be saved in a RAM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image register must be written first so that, if an in-
terrupt occurs between the two instructions, the
DWR is not affected.
Figure 6. Data read-only memory Window Memory Addressing
DATA ROM
13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROGRAM SPACE ADDRESS
WINDOW REGISTER 7 6 5 4 3 2 1 0
READ
CONTE NT S
(DWR)
5 4 3 2 1 0 DATA SPACE ADDRESS
01
40h-7Fh
IN INSTRUCTION
Example:
DWR=28h
0 10 1 0 0 0
DATA SPACE ADDRESS
01 0 1100 1
59h
ROM
ADDRESS:A19h
0 10 1 0 0 0 0 1 1 0 0 1
VR0 A15 73
11/86
115
11 Page | ||
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| PDF Descargar | [ Datasheet ST62E32B.PDF ] | |
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