ZL30105 반도체 회로 부품 판매점
T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer
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 Zarlink Semiconductor |
www.DataSheet4U.com
ZL30105
T1/E1/SDH Stratum 3 Redundant System Clock
Synchronizer for AdvancedTCA™ and H.110
Data Sheet
Features
• Synchronizes to clock-and-sync-pair to maintain
minimal phase skew between the master-clock
and the redundant slave-clock
• Supports ITU-T G.813 option 1, G.823 for
2048 kbit/s and G.824 for 1544 kbit/s interfaces
• Supports Telcordia GR-1244-CORE Stratum
3/4/4E
• Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
• Accepts three input references and synchronizes
to any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
• Provides a range of clock outputs: 1.544 MHz
(DS1), 2.048 MHz (E1), 3.088 MHz, 16.384 MHz,
and 19.44 MHz (SDH), and either 4.096 MHz and
8.192 MHz or 32.768 MHz and 65.536 MHz, and a
choice of 6.312 MHz (DS2), 8.448 MHz (E2),
44.736 MHz (DS3) or 34.368 MHz (E3)
• Provides 5 styles of 8 kHz framing pulses and a
2 kHz multi-frame pulse
• Holdover frequency accuracy of 1x10-8
• Selectable loop filter 1.8 Hz, 3.6 Hz or 922 Hz
• Less than 24 psrms intrinsic jitter on the 19.44 MHz
output clock, compliant with GR-253-CORE OC-3
and G.813 STM-1 specifications
November 2005
Ordering Information
ZL30105QDG 64 pin TQFP Trays
ZL30105QDG1 64 pin TQFP* Trays Bake & Drypack
* Pb Free Matte Tin
-40°C to +85°C
• Less than 0.6 nspp intrinsic jitter on all output
clocks and frame pulses
• Manual or Automatic hitless reference switching
between any combination of valid input reference
frequencies
• Provides Lock, Holdover and selectable Out of
Range indication
• Simple hardware control interface
• Selectable external master clock source: Clock
Oscillator or Crystal
Applications
• Synchronization and timing control for multi-trunk
SDH and T1/E1 systems such as DSLAMs,
Gateways and PBXs
• Clock and frame pulse source for
AdvancedTCA™- and other time division
multiplex (TDM) buses
OSCi OSCo TIE_CLR
FASTLOCK LOCK
OUT_SEL2
REF0
REF1
REF2
REF2_SYNC
REF_FAIL0
REF_FAIL1
REF_FAIL2
REF_SEL1:0
RST
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
TIE
Corrector
Enable
State Machine
Mode
Control
Frequency
Select
MUX
DS1
Synthesizer
SDH
Synthesizer
Programmable
Synthesizer
IEEE
1149.1a
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
C3o
C19o
F2ko
C6/8.4/34/44o
OUT_SEL1:0
TRST
MODE_SEL1:0
HMS HOLDOVER SEC_MSTR APP_SEL1:0
TCK TDI TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30105
Data Sheet
Description
The ZL30105 SDH/PDH System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing
and synchronization for SDH and T1/E1 transmission equipment. It provides advanced support for systems
deploying redundant clocks.
The ZL30105 generates SBI, ST-BUS and other TDM clock and framing signals that are phase locked to one of
three network references or to a system master-clock reference. It helps ensure system reliability by monitoring its
references for frequency accuracy and stability and by maintaining tight phase alignment between the master-clock
and slave-clock outputs even in the presence of high network jitter.
The ZL30105 is intended to be the central timing and synchronization resource for network equipment that
complies with ITU-T, Telcordia, ETSI and ANSI network specifications.
2
Zarlink Semiconductor Inc.
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국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
[ 홈페이지 ]
IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈
( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )
전력반도체 문의 : 010-3582-2743
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