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PDF ST62E35B Data sheet ( Hoja de datos )

Número de pieza ST62E35B
Descripción (ST62E35B / ST62T35B) 8-BIT OTP/EPROM MCUs
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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R ST62T35B/E35B
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
s -40 to +125°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 192 bytes
s Data EEPROM: 128 bytes
s User Programmable Options
s 36 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
s 12 I/O lines can sink up to 20mA to drive LEDs
or TRIACs directly
s 8-bit Timer/ Counter with 7-bit programmable
prescaler
s 16-bit Auto-reload Timer with 7-bit
programmable prescaler (AR Timer)
s Digital Watchdog
s 8-bit A/D Converter with 24 analog inputs
s 8-bit Synchronous Peripheral Interface (SPI)
s 8-bit Asynchronous Peripheral Interface
(UART)
s On-chip Clock oscillator can be driven by Quartz
Crystal or Ceramic resonator
s Oscillator Safe Guard
s One external Non-Maskable Interrupt
s ST623x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
DEVICE
ST62T35B
ST62E35B
OTP
(Bytes)
7948
-
EPROM
(Bytes)
-
7948
I/O Pins
36
36
PQFP52
CQFP52W
(See end of Datasheet for Ordering Information)
Rev. 2.3
March 1998
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ST62E35B pdf
ST62T35B/E35B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T35B and ST62E35B devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which is targeted at low to me-
dium complexity applications. All ST62xx devices
are based on a building block approach: a com-
Figure 1. Block Diagram
mon core is surrounded by a number of on-chip
peripherals.
The ST62E35B is the erasable EPROM version of
the ST62T35B device, which may be used to em-
ulate the ST62T35B device, as well as the respec-
tive ST6235B ROM devices.
TEST/ VPP
NMI
T EST
8-BIT
A/D CONVERTER
INTERRUPT
PRO GRAM
Memory
79 48 bytes
DATA ROM
USER
SELEC TABLE
DATA RAM
192 Bytes
DATA EEPROM
128 Bytes
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8 BIT CORE
POWER
SUP PLY
OSCILLATOR
RESE T
PORT A
PORT B
PORT C
PORT D
UAR T
PORT E
AUTORELOAD
TIMER
TIM ER
SPI (SERIA L
PERIPHER AL
INTERF ACE)
DIGI TAL
WATCHDO G
PA0..PA1 / 20 mA Sink
PA2/OVF/ 20 mA Sink
PA3/PWM/20 mA Sink
PA4/Ain/CP 1
PA 5/Ain/CP2
PA 6...PA7/Ain
PB 0..PB7/Ain
PC4..PC7/Ain
PD0,PD 6,PD7/Ain
PD1/Ain/Scl
PD2/Ain/Si n
PD3/Ain/Sout
PD4/Ain/R XD1
PD5/Ain/TX D1
PE0...PE7
TIMER
VDDVSS OSCin OSCout RESE T
(VPP on EPROM/OTP versions only)
VR01823E
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ST62E35B arduino
ST62T35B/E35B
MEMORY MAP (Cont’d)
1.3.5 Data Window Register (DWR)
Data Window Register (DWR)
The Data read-only memory window is located
from address 0040h to address 007Fh in Data
space. It allows direct reading of 64 consecutive
bytes located anywhere in program memory, be-
tween address 0000h and 1FFFh (top memory ad-
dress depends on the specific device). All the pro-
gram memory can therefore be used to store either
instructions or read-only data. Indeed, the window
can be moved in steps of 64 bytes along the pro-
gram memory by writing the appropriate code in the
Data Window Register (DWR).
The DWR can be addressed like any RAM loca-
tion in the Data Space, it is however a write-only
register and therefore cannot be accessed using
single-bit operations. This register is used to posi-
tion the 64-byte read-only data window (from ad-
dress 40h to address 7Fh of the Data space) in
program memory in 64-byte steps. The effective
address of the byte to be read as data in program
memory is obtained by concatenating the 6 least
significant bits of the register address given in the
instruction (as least significant bits) and the con-
tent of the DWR register (as most significant bits),
as illustrated in Figure 5 below. For instance,
when addressing location 0040h of the Data
Space, with 0 loaded in the DWR register, the
physical location addressed in program memory is
00h. The DWR register is not cleared on reset,
therefore it must be written to prior to the first ac-
cess to the Data read-only memory window area.
Address: 0C9h — Write Only
70
- DWR6 DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
Bits 7 = Not used.
Bit 6-0 = DWR5-DWR0: Data read-only memory
Window Register Bits. These are the Data read-
only memory Window bits that correspond to the
upper bits of the data read-only memory space.
Caution: This register is undefined on reset. Nei-
ther read nor single bit instructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while exe-
cuting an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossible to avoid writ-
ing to the DWR during the interrupt service rou-
tine, an image of the register must be saved in a
RAM location, and each time the program writes
to the DWR, it must also write to the image regis-
ter. The image register must be written first so
that, if an interrupt occurs between the two instruc-
tions, the DWR is not affected.
Figure 5. Data read-only memory Window Memory Addressing
DATA ROM
13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROGRAM SPACE ADDRESS
WINDOW REGISTER 7 6 5 4 3 2 1 0
READ
CONTENTS
(DWR)
5 4 3 2 1 0 DATA SPACE ADDRESS
01
40h-7Fh
IN INSTRUCTION
Example:
DWR=28h
0 10 10 0 0
DATA SPACE ADDRESS
01 0 1100 1
59h
ROM
ADDRESS:A19h
0 10 10 0 0 0 1 1 0 0 1
VR0A 157 3
11/82
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