ZL30119 판매점 - Low Jitter Line Card Synchronizer

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ZL30119

SONET/SDH

Low Jitter Line Card Synchronizer

Data Sheet

A full Design Manual is available to qualified customers.

To register, please send an email to

[email protected].

Features

• Synchronizes with standard telecom system

references and synthesizes a wide variety of

protected telecom line interface clocks that are

compliant with Telcordia GR-253-CORE and ITU-T

G.813

• Internal APLL provides standard output clock

frequencies from 6.48 MHz up to 622.08 MHz with

jitter less than 1 ps RMS for OC-48/STM-16

interfaces

• Programmable output synthesizers (P0, P1)

generate clock frequencies from any multiple of

8 kHz up to 77.76 MHz in addition to 2 kHz

• Provides two DPLLs which are independently

configurable through a serial peripheral interface

• DPLL1 provides all the features necessary for

generating SONET/SDH compliant clocks including

automatic hitless reference switching, automatic

mode selection (locked, free-run, holdover), and

selectable loop bandwidth

Ordering Information

December 2005

ZL30119GGG 100 Pin CABGA Trays

ZL30119GGG2 100 Pin CABGA* Trays

*Pb Free Tin/Silver/Copper

-40oC to +85oC

• DPLL2 provides a comprehensive set of features

for generating derived output clocks and other

general purpose clocks

• Provides 8 reference inputs which support clock

frequencies with any multiples of 8 kHz up to

77.76 MHz in addition to 2 kHz

• Provides 3 sync inputs for output frame pulse

alignment

• Generates several styles of output frame pulses

with selectable pulse width, polarity, and frequency

• Configurable input to output delay, and output to

output phase alignment

• Flexible input reference monitoring automatically

disqualifies references based on frequency and

phase irregularities

• Supports IEEE 1149.1 JTAG Boundary Scan

osco

osci

ref0

ref1

ref2

ref3

ref4

ref5

ref6

ref7

sync0

sync1

sync2

int_b

trst_b tck tdi tms tdo dpll2_ref

dpll1_hs_en dpll1_lock dpll1_holdover diff0_en diff1_en

Master

Clock

IEEE 1449.1

JTAG

ref7:0

sync2:0

Reference ref_&_sync_status

Monitors

DPLL2

ref

DPLL1

sync

fb_clk/fp

Synthesizer

SONET/SDH

APLL

Feedback

Synthesizer

p0_clk0

p0_clk1

p0_fp0

p0_fp1

p1_clk0

p1_clk1

diff0

diff1

sdh_clk0

sdh_clk1

sdh_fp0

sdh_fp1

fb_clk

SPI Interface

Controller &

State Machine

sck si so cs_b

rst_b

dpll1_mod_sel1:0

sdh_filter filter_ref0 filter_ref1

Figure 1 - Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL30119 반도체 회로 부품 판매점

Low Jitter Line Card Synchronizer

국내 전력반도체 판매점

일반적인 전자부품 판매점

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