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3D3220 반도체 회로 부품 판매점

MONOLITHIC 10-TAP FIXED DELAY LINE



Data Delay Devices 로고
Data Delay Devices
3D3220 데이터시트, 핀배열, 회로
www.DataSheet4U.com
MONOLITHIC 10-TAP
FIXED DELAY LINE
(SERIES 3D3220)
3D3220
FEATURES
PACKAGES
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
IN 1
N/C 2
O2 3
14 VDD
13 O1
12 O3
IN 1 14 VDD
N/C 2 13 O1
O2 3 12 O3
O4 4 11 O5
O6 5 10 O7
O8 6 9 O9
Low ground bounce noise
O4 4 11 O5
GND 7 8 O10
Leading- and trailing-edge accuracy
O6 5 10 O7
3D3220D-xx SOIC
Delay range: 0.75ns through 7000ns
Delay tolerance: 2% or 0.5ns
Temperature stability: ±2% typical (-40C to 85C)
O8 6
GND 7
9 O9
8 O10
IN 1
N/C 2
N/C 3
O2 4
16 VDD
15 N/C
14 O1
13 O3
Vdd stability: ±1% typical (3.0V-3.6V)
Minimum input pulse width: 15% of total delay
3D3220-xx DIP
3D3220G-xx Gull-Wing
O4 5
O6 6
O8 7
12 O5
11 O7
10 O9
14-pin Gull-Wing available as drop-in
replacement for hybrid delay lines
For mechanical dimensions, click here.
For package marking details, click here.
GND 8
9 O10
3D3220S-xx SOL
FUNCTIONAL DESCRIPTION
The 3D3220 10-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 0.75ns through 700ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D3220 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.
The all-CMOS 3D3220 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is
offered in a standard 14-pin auto-insertable DIP and space saving
surface mount 14-pin SOIC and 16-pin SOL packages.
PIN DESCRIPTIONS
IN
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
VDD
GND
Delay Line Input
Tap 1 Output (10%)
Tap 2 Output (20%)
Tap 3 Output (30%)
Tap 4 Output (40%)
Tap 5 Output (50%)
Tap 6 Output (60%)
Tap 7 Output (70%)
Tap 8 Output (80%)
Tap 9 Output (90%)
Tap 10 Output (100%)
+3.3 Volts
Ground
TABLE 1: PART NUMBER SPECIFICATIONS
DASH
NUMBER
-.75
-1
-1.5
-2
-2.5
-4
-5
-10
-20
-50
-100
-700
TOLERANCES
TOTAL
TAP-TAP
DELAY (ns) DELAY (ns)
6.75 ± 0.5*
0.75 ± 0.4
9.0 ± 0.5*
1.0 ± 0.5
13.5 ± 0.5*
1.5 ± 0.7
18.0 ± 0.5*
2.0 ± 0.8
22.5 ± 0.5*
2.5 ± 1.0
36.0 ± 0.7*
4.0 ± 1.3
50.0 ± 1.0
5.0 ± 1.5
100.0 ± 2.0
10.0 ± 2.0
200.0 ± 4.0
20.0 ± 4.0
500.0 ± 10
50.0 ± 10
1000 ± 20
100 ± 20
7000 ± 140
700 ± 140
Rec’d Max
Frequency
28.4 MHz
23.8 MHz
18.0 MHz
14.5 MHz
12.1 MHz
8.33 MHz
6.67 MHz
3.33 MHz
1.67 MHz
0.67 MHz
0.33 MHz
0.05 MHz
INPUT RESTRICTIONS
Absolute Max Rec’d Min
Frequency
Pulse Width
166.7 MHz
17.6 ns
166.7 MHz
21.0 ns
166.7 MHz
27.8 ns
166.7 MHz
34.5 ns
125.0 MHz
41.2 ns
133.3 MHz
60.0 ns
66.7 MHz
75.0 ns
33.3 MHz
150 ns
16.7 MHz
300 ns
6.67 MHz
750 ns
3.33 MHz
1500 ns
0.48 MHz
10500 ns
Absolute Min
Pulse Width
3.00 ns
3.00 ns
3.00 ns
3.00 ns
4.00 ns
6.00 ns
7.50 ns
15.0 ns
30.0 ns
75.0 ns
150 ns
1050 ns
* Total delay referenced to Tap1 output; Input-to-Tap1 = 7.5ns ± 1.0ns
NOTE: Any dash number between .75 and 700 not shown is also available as standard.
2005 Data Delay Devices
Doc #05001
12/22/05
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1


3D3220 데이터시트, 핀배열, 회로
3D3220
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D3220 ten-tap delay line architecture is
shown in Figure 1. The delay line is composed of
a number of delay cells connected in series.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time. The
delay cells are matched and share the same
compensation signals, which minimizes tap-to-
tap delay deviations over temperature and supply
voltage variations.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Maximum and
an Absolute Maximum operating input frequency
and a Minimum and an Absolute Minimum
operating pulse width have been specified.
OPERATING FREQUENCY
The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
The Maximum Operating Frequency specification
determines the highest frequency of the delay
line input signal for which the output delay
accuracy is guaranteed.
To guarantee the Table 1 delay accuracy for
input frequencies higher than the Maximum
Operating Frequency, the 3D3220 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY DEVICES
be consulted.
OPERATING PULSE WIDTH
The Absolute Minimum Operating Pulse Width
(high or low) specification, tabulated in Table 1,
determines the smallest Pulse Width of the delay
line input signal that can be reproduced, shifted
in time at the device output, with acceptable
pulse width distortion.
The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.
To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D3220 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the part number will include a
IN O1 O2 O3 O4 O5 O6 O7 O8 O9 O10
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
Temp & VDD
Compensation
VDD
Figure 1: 3D3220 Functional Diagram
GND
Doc #05001
12/22/05
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2




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